IP Library Granted Patent US 10,402,113
Granted Patent B2
US 10,402,113 · App. 15/313,690 · Granted Sep 3, 2019

Live migration of data

Inventors: Harvey Ray (Frederick, CO); Derek Alan Sherlock (Boulder, CO); Gregg B. Lesartre (Fort Collins, CO)
Assignee: Hewlett Packard Enterprise Development LP
G06F3/0647G06F3/065G06F3/0619G06F3/0656G06F3/0683G06F11/108
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Quick Facts
Patent No.
US 10,402,113
App. No.
15/313,690
Granted
Sep 3, 2019
Kind
B2
Abstract

According to an example, hierarchal stripe locks may be obtained for a source stripe and a destination stripe. In response to receiving data for the source stripe, the data is written from the source stripe to the destination stripe, and the hierarchal stripe locks are released for the source stripe and the destination stripe. In response to receiving the data-migrated token, the hierarchal stripe locks are released for the source stripe and the destination stripe.

Claims (53)

1. A method for live migration of data from a source stripe to a destination stripe, the method comprising:

obtaining, by a redundancy controller, hierarchal stripe locks for the source stripe and the destination stripe;

receiving a data-migrated token or the data from the source stripe;

in response to receiving the data,

writing the data from the source stripe to the destination stripe,

writing a data-migrated token to the source stripe, and

releasing the hierarchal stripe locks for the source stripe and the destination stripe; and

in response to receiving a data-migrated token indicating the data is already migrated from the source stripe, releasing the hierarchal stripe locks for the source stripe and the destination stripe;

wherein obtaining the hierarchal stripe locks comprises ordering one of the hierarchal stripe locks as a primary stripe lock and another of the hierarchal stripe locks as a secondary stripe lock, and obtaining the primary stripe lock prior to the secondary stripe lock.

2. The method of claim 1 , comprising staging an entry into the live migration of the data, wherein a first stage comprises:

arming reads for each distributed redundancy controller, wherein the armed reads for each distributed redundancy controller are to redirect each read to the destination stripe when the data-migrated token indicating the data is already migrated from the source stripe.

3. The method of claim 2 , wherein the staging comprises a second stage and the second stage comprises:

arming writes for each of the distributed redundancy controllers, wherein each write performed by a distributed redundancy controller is to:

obtain the hierarchal stripe locks for the source stripe and the destination stripe,

write the data to the destination stripe,

write the data-migrated token to the source stripe, and

release the hierarchal stripe locks for the source stripe and the destination stripe.

4. The method of claim 1 , comprising staging an exit from the live migration of the data, wherein staging the exit comprises:

determining that the data migrated token is received for all source stripes in a source memory buffer; and

updating each of the distributed redundancy controllers to only access the destination stripes in a destination memory buffer.

5. The method of claim 1 , wherein the ordering of one of the hierarchal stripe locks is based on stripe numbers and identification numbers of media controllers for the source stripe and the destination stripe.

6. A computing device for live migration of data from a source stripe to a destination stripe, comprising a hardware redundancy controller to:

acquire hierarchal stripe locks for the source stripe and the destination stripe;

receive one of the data and a data-migrated token from the source stripe;

copy the data from the source stripe to the destination stripe and release the hierarchal stripe locks for the source stripe and the destination stripe if the data is received from the source stripe; and

release the hierarchal stripe locks for the source stripe if the data-migrated token is received from the source strip;

wherein the hardware redundancy controller is to arm each distributed redundancy controller to redirect reads to the destination stripe when the data-migrated token is received as a first stage prior to the live migration of data.

7. The computing device of claim 6 , wherein to copy data from the source stripe to the destination stripe, the hardware redundancy controller is to write a data-migrated token to the source stripe.

8. The computing device of claim 6 , wherein the hardware redundancy controller is to arm writes for each of the distributed redundancy controllers, wherein each write is to acquire the hierarchal stripe locks for the source stripe and the destination stripe, copy the data from the source stripe to the destination stripe, write the data-migrated token to the source stripe, and release the hierarchal stripe locks for the source stripe and the destination stripe as a second stage prior to the live migration of data.

9. The computing device of claim 6 , wherein the hardware redundancy controller is to determine that the data-migrated token is received for all source stripes in a source memory buffer and update each of the distributed redundancy controllers to only access the destination stripes in a destination memory buffer subsequent to the live migration of data.

10. The computing device of claim 6 , wherein to acquire the hierarchal stripe locks, the hardware redundancy controller is to:

order one of the hierarchal stripe locks as a primary stripe lock and another of the hierarchal stripe locks as a secondary stripe lock; and

acquire the primary stripe lock prior to the secondary stripe lock.

11. A system comprising:

a plurality of redundancy controllers;

a plurality of memory modules each including a media controller and a memory, wherein the memory modules are connected to the plurality of redundancy controllers through a memory bus,

wherein each of the redundancy controllers is to:

initiate, by a migration engine, the live migration of data from a source stripe to a destination stripe, wherein the source stripe and the destination stripe are in at least one of the plurality of memory modules;

acquire, by a stripe locking module, hierarchal stripe locks for a source stripe and a destination stripe; and

receive data-migrated token or the data for the source stripe,

wherein in response to receiving the data for the source stripe, write the data from the source stripe to the destination stripe, write a data-migrated token to the source stripe, update a parity for the source stripe and the destination stripe, and release the hierarchal stripe locks for the source stripe and the destination stripe, and

wherein in response to receiving the data-migrated token, release the hierarchal stripe locks for the source stripe and the destination stripe.

12. The system of claim 11 , each of the redundancy controllers is to stage an entry into the live migration of the data, wherein to stage the entry is to:

arm reads for each distributed redundancy controller, wherein the armed reads for each distributed redundancy controller are to redirect each read to the destination stripe when the data-migrated token is received; and

arm writes for each of the distributed redundancy controllers, wherein each write by a distributed redundancy controller is to:

obtain the hierarchal stripe locks for the source stripe and the destination stripe,

write the data from the source stripe to the destination stripe,

write the data-migrated token to the source stripe,

update the parity for the source stripe and the destination stripe, and

release the hierarchal stripe locks for the source stripe and the destination stripe.

13. The system of claim 11 , wherein the each of the redundancy controllers is to stage an exit from the live migration of the data, wherein to stage the exit is to:

determine that the data-migrated token is received for all source stripes in a source memory buffer; and

update each of the distributed redundancy controllers to only access the destination stripes in a destination memory buffer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2017
From: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 041315/0182 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 15, 2016
From: RAY, HARVEY; SHERLOCK, DEREK ALAN; LESARTRE, GREGG B.
To: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Reel/Frame 040638/0344 →
Continuity (1)
Related Publication 20170192714A1 · Jul 6, 2017
Cited By (1)
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