IP Library › Granted Patent US 10,402,335
Granted Patent B2
US 10,402,335 · App. 15/476,126 · Granted Sep 3, 2019

Method and apparatus for persistently caching storage data in a page cache

Inventors: Sanjay K. Kumar (Hillsboro, OR); Dheeraj R. Subbareddy (Portland, OR); Jeffrey R. Jackson (Newberg, OR)
Assignee: Intel Corporation
G06F12/0873G06F12/0238G06F12/0802G06F12/0804G06F12/0866G06F12/0871G06F16/172G06F21/55G06F21/76G06F2212/1041G06F2212/225G06F2212/283G06F2212/608
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Quick Facts
Patent No.
US 10,402,335
App. No.
15/476,126
Granted
Sep 3, 2019
Kind
B2
Abstract

In one embodiment, an apparatus comprises a memory to store executable instructions of an operating system and a processor to identify a request for data from an application; determine whether a persistent page cache stores a copy of the data, wherein the persistent page cache is directly addressable by the processor and is to cache data of a storage device that is not directly addressable by the processor; and access the data from the persistent page cache.

Claims (62)

1. An apparatus comprising:

a processor comprising circuitry, the processor configured to:

implement a first file system that is to send first data requests towards a volatile page cache;

implement a second file system that is to send second data requests towards a persistent page cache;

identify a request for first data from an application;

determine whether the persistent page cache stores a copy of the first data, wherein the persistent page cache is directly addressable by the processor and is to cache second data of a storage device that is not directly addressable by the processor; and

access the first data from the persistent page cache.

2. The processor of claim 1 , wherein the processor is to:

identify a request for third data from a second application;

determine whether the volatile page cache stores a copy of the third data, wherein the volatile page cache is directly addressable by the processor and is to cache fourth data of the storage device; and

access the third data from the volatile page cache.

3. The processor of claim 1 , wherein the processor is to:

implement a volatile page cache manager that is to determine that a file that includes the first data is marked for caching in the persistent page cache; and

send a request for the first data to a persistent page cache manager.

4. The processor of claim 1 , wherein the first file system is to:

determine whether a file that includes the first data is marked for caching in the persistent page cache or volatile page cache; and

in response to determining that the file is marked for caching in the persistent page cache, send a request for the first data to the second file system.

5. The processor of claim 1 , wherein the processor is to:

implement a shim layer that is to intercept a data request sent to the first file system and communicate the data request to the second file system.

6. The processor of claim 1 , wherein the processor is to determine whether to cache data in the volatile page cache or the persistent page cache based on at least one of:

a hint from an application that issues a system call referencing the data to be cached;

whether the data to be cached is opened for writing;

whether the data to be cached is required for booting; or

whether the data to be cached is file data or metadata.

7. The processor of claim 1 , wherein the processor is to send a request to the storage device to copy the first data to the persistent page cache upon a determination that the persistent page cache does not store a copy of the first data.

8. The processor of claim 7 , wherein the processor is to translate a file descriptor and offset of the request for data into a logical block address and send the logical block address to the storage device in the request to the storage device.

9. The processor of claim 1 , wherein the volatile page cache is to be stored in a volatile memory that is further to store application code and application data.

10. The processor of claim 1 , wherein the processor is to, upon receiving a request to sync dirty data of the persistent page cache, update metadata in the persistent page cache to mark the dirty data as persistent.

11. A non-transitory machine readable storage medium having instructions stored thereon, the instructions when executed by a processor to cause the processor to:

implement a first file system that is to send data requests towards a volatile page cache;

implement a second file system that is to send data requests towards a persistent page cache;

identify a request for first data from an application;

determine whether the persistent page cache stores a copy of the first data, wherein the persistent page cache is directly addressable by the processor and is to cache second data of a storage device that is not directly addressable by the processor; and

access the first data from the persistent page cache.

12. The storage medium of claim 11 , wherein the instructions when executed are to further cause the processor to:

identify a request for third data from a second application;

determine, whether the volatile page cache stores a copy of the third data, wherein the volatile page cache is directly addressable by the processor and is to cache fourth data of the storage device; and

access the third data from the volatile page cache.

13. The storage medium of claim 11 , wherein the instructions when executed are to further cause the processor to:

implement a volatile page cache manager that is to determine that a file that includes the first data is marked for caching in the persistent page cache; and

send a request for the first data to a persistent page cache manager.

14. The storage medium of claim 11 , wherein the instructions when executed are to further cause the processor to implement the first file system of an operating system, wherein the first file system is to:

determine whether a file that includes the first data is marked for caching in the persistent page cache or volatile page cache; and

in response to determining that the file is marked for caching in the persistent page cache, send a request for the first data to the second file system.

15. The storage medium of claim 11 , wherein the instructions when executed are to further cause the processor to:

implement a shim layer that is to intercept a data request sent to the first file system and communicate the data request to the second file system.

16. A computer system comprising:

a volatile memory to store a volatile page cache;

a persistent memory to store a persistent page cache; and

a processor configured to:

implement a first file system that is to send first data requests towards the volatile page cache;

implement a second file system that is to send second data requests towards the persistent page cache;

identify a request for first data from an application;

determine whether the persistent page cache stores a copy of the first data, wherein the persistent page cache is directly addressable by the processor and is to cache second data of a storage device that is not directly addressable by the processor; and

access the first data from the persistent page cache.

17. The computer system of claim 16 , wherein the processor is to:

identify a request for third data from a second application;

determine whether the volatile page cache stores a copy of the third data, wherein the volatile page cache is directly addressable by the processor and is to cache fourth data of the storage device; and

access the third data from the volatile page cache.

18. The computer system of claim 16 , wherein the volatile page cache is to be stored in a volatile memory that is further to store application code and application data.

19. The computer system of claim 16 , further comprising the storage device.

20. The computer system of claim 16 , further comprising one or more of: a battery communicatively coupled to the processor, a display communicatively coupled to the processor, or a network interface communicatively coupled to the processor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 13, 2017
From: JACKSON, JEFFREY R.; KUMAR, SANJAY K.; SUBBAREDDY, DHEERAJ R.
To: INTEL CORPORATION
Reel/Frame 041995/0208 →
Continuity (1)
Related Publication 20180285276A1 · Oct 4, 2018