Hybrid flash memory structure
A memory system includes a code flash and data flash merged flash memory, which may contain a code flash with differential cell structure, a data flash with single cell structure, decoder circuitry, a sense amplifier, and other suitable support circuitry. The code flash and data flash may be located in a same plane or multi planes. In some examples, the code flash may be also accessed to read while the data flash is performing write operation, and vice versa.
1. A hybrid flash memory device comprising:
a code flash memory comprising differential memory cells;
a data flash memory comprising single memory cells; and
support circuitry comprising at least a decoder, a sense amplifier, logic circuitry, and a flag register, the flag register comprising a plurality of bits corresponding to the multiple sectors of the hybrid flash memory device and each of the plurality of bits representing a configuration of a corresponding flash memory sector.
2. The device of claim 1 , wherein the code flash memory is fast access memory and the data flash memory is high density memory.
3. The device of claim 1 , wherein the decoder comprises an x-decoder and a y-decoder.
4. The device of claim 1 , wherein
the code flash memory is configured to be accessed for a read operation while the data flash memory is performing a write operation; and
the code flash memory is configured to perform a write operation while the data flash memory is being accessed for a read operation.
5. The device of claim 1 , wherein the code flash memory and the data flash memory are on a same plane and configured to share the support circuitry.
6. The device of claim 1 , wherein the code flash memory and the data flash memory are on different planes and at least a portion of the support circuitry is dedicated to the code flash memory and the data flash memory, respectively.
7. The device of claim 1 , wherein the code flash memory is configured to store one or more of a boot code, a wake-up code, and an executable code for a computing system.
8. The device of claim 1 , wherein the code flash memory and the data flash memory include SONOS transistor cells, floating gate cells, eFlash cells, pFlash cells, 1T/1R resistive RAMs, resistive memory based cells, phase change memory based cells, ferroelectric RAM based cells, ferroelectric capacitor based cells, or magnetic RAM based cells.
9. A hybrid flash memory device comprising:
a flash memory comprising multiple sectors, wherein each sector is configurable as one of a code flash memory with differential memory cells and a data flash memory with single memory cells;
a flag register comprising a plurality of bits corresponding to the multiple sectors of the flash memory and each of the plurality of bits representing a configuration of a corresponding flash memory sector; and
support circuitry comprising at least a decoder, a sense amplifier, and logic circuitry.
10. The device of claim 9 , wherein a flash memory sector is re-configurable by setting a value of a corresponding bit in the flag register.
11. The device of claim 9 , wherein
when a flash sector is configured as the data flash memory, the flash sector uses a single cell structure; and
when the flash sector configured as the code flash memory, the flash sector uses a differential cell structure.
12. The device of claim 9 , wherein
when a flash sector is configured as the data flash memory, a read access speed for the flash sector is set to a slow speed; and
when the flash sector configured as the code flash memory, the read access speed is set to a slow speed.
13. The device of claim 9 , wherein the support circuitry is configured to support all sectors of the flash memory.
14. A hybrid flash memory device comprising:
a code flash memory comprising differential memory cells, wherein the code flash memory is fast access memory;
a data flash memory comprising single memory cells, wherein the data flash memory is high density memory; and
support circuitry comprising at least a decoder, a sense amplifier, logic circuitry, and a flag register, the flag register comprising a plurality of bits corresponding to the multiple sectors of the hybrid flash memory device and each of the plurality of bits representing a configuration of a corresponding flash memory sector.
15. The device of claim 14 , wherein each input/output (I/O) includes multiple columns of bitlines and a pair of DLE/DLO data lines coupled to the sense amplifier.
16. The device of claim 15 , wherein the DLE/DLO datalines are connected to the bitlines through a y-decode signal.
17. The device of claim 14 , wherein sense amplifier includes a reference current mirror to generate a reference current for single cell operation.
18. The device of claim 17 , wherein sense amplifier further includes a switcher to select the DLE or DLO datalines as a reference side while another side is a cell side.
19. The device of claim 17 , wherein the reference current mirror is turned off for a differential cell operation.