IP Library Granted Patent US 10,404,097
Granted Patent B2
US 10,404,097 · App. 15/399,765 · Granted Sep 3, 2019

Multi-input line-redundant uninterruptable power supply

Inventors: Douglas P. Arduini (San Ramon, CA); Sung Kee Baek (San Ramon, CA); Richard Anthony O'Brien (Livermore, CA); John Beecroft (Camarillo, CA); M. Baris Dogruoz (Santa Clara, CA)
Assignee: Cisco Technology, Inc.
H02J9/061H02M3/04H02M7/04H02M2001/007
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Quick Facts
Patent No.
US 10,404,097
App. No.
15/399,765
Granted
Sep 3, 2019
Kind
B2
Abstract

A power supply system may comprise a plurality of input buses and an output bus. A plurality of multi-input power supplies may be disposed between the plurality of input buses and the output bus. The plurality of multi-input power supplies may be configured to supply a predetermined amount of power to the output bus before and after a failure event. The failure event may comprise at least one of the following: a failure of a one of the plurality of multi-input power supplies and loss of power on one of the plurality of input buses. Each input to the power supply may include an independent power section to support near or full output power in the event of another input power loss. Any input line loss from an independent power bus/grid may provide line redundancy to the power supply and to the power system as an Uninterruptable Power Supply.

Claims (30)

1. An apparatus comprising:

a plurality of input buses;

an output bus; and

a plurality of multi-input power supplies, wherein each of the plurality of multi-input power supplies is connected to the plurality of input buses, wherein each of the plurality of the multi-input power supplies is connected to the output bus, the plurality of multi-input power supplies being configured to supply a predetermined amount of power to the output bus before and after a failure event comprising at least one of the following: a failure of a one of the plurality of multi-input power supplies and loss of power on one of the plurality of input buses, wherein the apparatus is configured to provide the predetermined amount of power to the output bus when power is lost on each of the plurality of input buses for a predetermined ride-through time, and wherein the ride-through time is function of a sum of a plurality of hold-up capacitors disposed in the plurality of multi-input power supplies.

2. The apparatus of claim 1 , wherein each of the plurality of multi-input power supplies comprises a plurality of sections, each one of the plurality of input buses being respectively connected to a different one of the plurality of sections.

3. The apparatus of claim 2 , wherein each of the plurality of sections comprises a first stage comprising an alternating current (AC) to direct current (DC) rectifier and converter.

4. The apparatus of claim 3 , wherein each of the plurality of sections comprises a second stage comprising a direct current (DC) to direct current (DC) converter and isolation transformer.

5. The apparatus of claim 4 , wherein each of the plurality of sections comprises a hold-up capacitor.

6. The apparatus of claim 5 , wherein the hold-up capacitor is disposed between the first stage and the second stage.

7. An apparatus comprising:

a plurality of inputs;

an output; and

a plurality of sections, each one of the plurality of inputs being respectively connected to each one of the plurality of sections, the apparatus being configured to supply a predetermined amount of power to the output before and after a failure event comprising loss of power on one of the plurality of inputs, wherein the apparatus is configured to provide the predetermined amount of power to the output when power is lost on each of the plurality of inputs for a predetermined ride-through time, and wherein the ride-through time is function of a sum of a plurality of hold-up capacitors disposed in the plurality of sections.

8. The apparatus of claim 7 , wherein each of the plurality of sections comprises a first stage.

9. The apparatus of claim 8 , wherein the first stage comprises an alternating current (AC) to direct current (DC) rectifier and converter.

10. The apparatus of claim 9 , wherein each of the plurality of sections comprises a second stage.

11. The apparatus of claim 10 , wherein the second stage comprises a direct current (DC) to direct current (DC) converter and isolation transformer.

12. The apparatus of claim 11 , wherein each of the plurality of sections comprises a hold-up capacitor.

13. The apparatus of claim 12 , wherein the hold-up capacitor is disposed between the first stage and the second stage.

14. The apparatus of claim 7 , wherein the plurality of sections share a common heat sink.

15. The apparatus of claim 7 , further comprising an output filter capacitor.

16. The apparatus of claim 7 , further comprising a multi-input power supply with ORing-diode field-effect transistor (FET).

17. An apparatus comprising:

a plurality of inputs;

an output;

a plurality of sections, each one of the plurality of inputs being respectively connected to each one of the plurality of sections, the apparatus being configured to supply a predetermined amount of power to the output through the plurality of sections, wherein the apparatus is configured to provide the predetermined amount of power to the output when power is lost on each of the plurality of inputs for a predetermined ride-through time; and

a plurality of hold-up capacitors respectively disposed in each of the plurality of sections, wherein the ride-through time is a function of a sum of a capacitance of each of the plurality of hold-up capacitors.

18. The apparatus of claim 17 , wherein the apparatus is configured to supply a predetermined amount of power to the output before and after a failure event comprising loss of power on one of the plurality of inputs.

19. The apparatus of claim 17 , wherein the plurality of sections share a common heat sink.

20. The apparatus of claim 17 , further comprising a multi-input power supply with ORing-diode field-effect transistor (FET).

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 6, 2017
From: ARDUINI, DOUGLAS P.; BAEK, SUNG KEE; O'BRIEN, RICHARD ANTHONY; BEECROFT, JOHN; DOGRUOZ, M. BARIS
To: CISCO TECHNOLOGY, INC.
Reel/Frame 040867/0748 →
Continuity (2)
Provisional Application 62276089 · Jan 7, 2016
Related Publication 20170201122A1 · Jul 13, 2017
Cited By (1)
US 12,575,054