Clock synchronization method and apparatus
View Patent ↗A clock synchronization apparatus and method, which perform clock synchronization by determining a clock offset and a network delay between a master and a slave in an IEEE 1588 system. The clock synchronization method and apparatus include observing a clock offset and a packet delay using a timing packet received from a master node; estimating a clock offset and a packet delay from the observed clock offset and the observed packet delay; and performing synchronization with the master node based on the clock offset and the packet delay.
1. A clock synchronization method of a clock synchronization apparatus, comprising:
obtaining time information including packet transmission and packet receiving time of master node and slave node through packet exchange between the master node and the slave node;
estimating a clock offset and a packet delay between the master node and the slave node; and
performing clock synchronization between the master node and the slave node based on the estimated clock offset and the packet delay, wherein the time information includes a first packet transmission time of the master node T 1,k , a first packet receiving time of the slave node C[T 2,k κ−1 ], a second packet transmission time of the slave node C[T 3,k κ−1 ] and a second packet receiving time of the master node T 4,k , wherein (k={1, 2, . . . , N}) and (x={0, 1, 2 . . . , N−1}) N being a natural number, and
wherein estimating the clock offset and the packet delay comprises:
defining a relation between a packet delay of a first packet ϕ s,k and a packet delay of a second packet ϕ d,k based on a Packet Delay Variation (PDV) between the first packet and the second packet ψ k ;
deriving a Dynamic Linear Model (DLM) for the PDV; and
estimating the clock offset and the packet delay based on the derived DLM.
2. The clock synchronization method according to claim 1 , wherein the relation between the packet delay of the first packet ϕ s,k and the packet delay of the second packet ϕ d,k is defined by the following Equation (1):
ϕ d,k =ϕ s,k +ψ k (1).
3. The clock synchronization method according to claim 2 , wherein deriving the DLM for the PDV comprises:
defining the packet delay of the first packet ϕ s,k and the packet delay of the second packet ϕ d,k by the following Equations (2) and (3), respectively, where T 2,k is a first packet receiving time of the master node, T 3,k is a second packet transmission time of the master node, a difference between ΔT 1,k and ΔT 2,k denotes a k-th PDV of the first packet in a k-th clock synchronization and a difference between ΔT 3,k and ΔT 4,k denotes a k-th PDV of the second packet in the k-th clock synchronization;
ϕ s,k =ϕ s,k−1 +ΔT 2,k −ΔT 1,k (2)
ϕ d,k =ϕ d,k−1 +ΔT 4,k −ΔT 3,k (3)
defining the first packet receiving time of the slave node C[T 2,k κ−1 ] and the second packet transmission time of the slave node C[T 3,k κ−1 ] by the following Equations (4) and (5), respectively, where δ k is a k-th clock offset in the k-th clock synchronization, f 0 and f c represent frequencies of a clock of the master node and the clock of the slave node respectively; and
C
[
T
2
,
k
κ
-
1
]
=
(
T
1
,
k
+
δ
k
)
+
f
c
,
k
f
0
ϕ
s
,
k
(
4
)
C
[
T
3
,
k
κ
-
1
]
=
(
T
1
,
k
+
δ
k
)
+
f
c
,
k
f
0
{
(
T
4
,
k
-
T
1
,
k
)
-
ϕ
d
,
k
}
(
5
)
deriving the DLM for the PDV by the following Equation (6), where
Δ
T
i
,
k
=
T
i
,
k
-
T
i
,
k
-
1
,
i
∈
{
1
,
4
}
,
Δ
C
[
T
j
,
k
κ
-
1
]
=
C
[
T
j
,
k
κ
-
1
]
-
C
[
T
j
,
k
-
1
κ
-
1
]
,
j
∈
{
2
,
3
}
,
Γ
k
=
[
ΔT
1
,
k
Δ
T
4
,
k
]
T
,
Ξ
k
=
[
Δ
C
[
T
2
,
k
κ
-
1
]
Δ
C
[
T
3
,
k
κ
-
1
]
]
T
·
ψ
k
=
ψ
k
-
1
+
[
11
]
Γ
k
+
f
0
f
c
,
k
[
-
1
-
1
]
Ξ
k
.
(
6
)
4. The clock synchronization method according to claim 3 , wherein estimating the clock offset and the packet delay comprises:
defining errors of the estimation of the packet delay of the first packet and the packet delay of the second packet by the following Equations (7) and (8);
ɛ
δ
,
k
=
1
2
f
0
{
(
f
c
,
k
-
f
0
)
(
T
4
,
k
-
T
1
,
k
)
-
f
c
,
k
ψ
k
}
(
7
)
ɛ
ϕ
,
k
=
1
2
f
0
{
f
c
,
k
ψ
k
-
(
f
c
,
k
-
f
0
)
(
T
4
,
k
-
T
1
,
k
)
}
(
8
)
modeling the clock offset {circumflex over (δ)} k new and the packet delay {circumflex over (ϕ)} s,k new considering the errors by the following Equations (9) and (10), respectively, n k refers to relative noise with respect to the clock of the slave node; and
δ
^
k
new
=
δ
^
k
1588
-
ɛ
δ
,
k
+
n
k
(
9
)
ϕ
^
s
,
k
new
=
f
0
f
c
,
k
(
ϕ
^
s
,
k
1588
-
ɛ
ϕ
,
k
+
n
k
)
,
where
δ
^
k
1588
=
(
C
[
T
2
,
k
k
-
1
]
-
T
1
,
k
)
-
ϕ
^
s
,
k
1588
and
ϕ
^
s
,
k
1588
=
1
2
{
(
T
4
,
k
-
C
[
T
3
,
k
κ
-
1
]
)
+
(
C
[
T
2
,
k
κ
-
1
]
-
T
1
,
k
)
}
,
(
10
)
estimating the clock offset and the packet delay by inputting the time information to the modeled clock offset {circumflex over (δ)} k new and the packet delay {circumflex over (ϕ)} s,k new .
5. The clock synchronization method according to claim 1 , wherein performing the clock synchronization comprises:
transmitting the estimated clock offset and the packet delay to the slave node so that the slave node modifies the clock of the slave node based on the estimated clock offset and the packet delay.
6. A clock synchronization apparatus, comprising:
an input unit configured to perform packet exchange between a master node and a slave node;
a controller configured to obtain time information including packet transmission and packet receiving time of the master node and the slave node through the packet exchange, estimate a clock offset and a packet delay between the master node and the slave node, and perform clock synchronization between the master node and the slave node based on the estimated clock offset and the packet delay, wherein the time information includes a first packet transmission time of the master node T 1,k , a first packet receiving time of the slave node C[T 2,k κ−1 ], a second packet transmission time of the slave node C[T 3,k κ−1 ] and a second packet receiving time of the master node T 4,k , wherein (k={1, 2 . . . N}) and (x={0, 1, 2 . . . N−1}) N being a natural number, and
wherein the controller defines a relation between a packet delay of a first packet ϕ s,k and a packet delay of a second packet ϕ d,k based on a Packet Delay Variation (PDV) ψ k , derives a Dynamic Linear Model (DLM) for the PDV and estimates the clock offset and the packet delay based on the derived DLM.
7. The clock synchronization apparatus according to claim 6 , wherein the controller defines the relation between the packet delay of the first packet ϕ 2,k and the packet delay of the second packet ϕ d,k is defined by the following Equation (11):
ϕ d,k =ϕ s,k +ψ k (11).
8. The clock synchronization apparatus according to claim 7 , wherein the controller defines the packet delay of the first packet ϕ s,k and the packet delay of the second packet ϕ d,k by the following Equations (12) and (13), respectively, where T 2,k is a first packet receiving time of the master node, T 3,k is a second packet transmission time of the master node, a difference between ΔT 1,k and ΔT 2,k denotes a k-th PDV of the first packet in a k-th clock synchronization and a difference between ΔT 3,k and ΔT 4,k denotes a k-th PDV of the second packet in the k-th clock synchronization;
ϕ s,k =ϕ s,k−1 +ΔT 2,k −ΔT 1,k (12)
ϕ d,k =ϕ d,k−1 +ΔT 4,k −ΔT 3,k (13)
defines the first packet receiving time of the slave node C[T 2,k κ−1 ] and the second packet transmission time of the slave node C[T 3,k κ−1 ] by the following Equations (14) and (15), respectively, where δ k is a k-th clock offset in the k-th clock synchronization, f 0 and f c represent frequencies of a clock of the master node and the clock of the slave node respectively; and
C
[
T
2
,
k
κ
-
1
]
=
(
T
1
,
k
+
δ
k
)
+
f
c
,
k
f
0
ϕ
s
,
k
(
14
)
C
[
T
3
,
k
κ
-
1
]
=
(
T
1
,
k
+
δ
k
)
+
f
c
,
k
f
0
{
(
T
4
,
k
-
T
1
,
k
)
-
ϕ
d
,
k
}
(
15
)
derives the DLM for the PDV by the following Equation (16), where
Δ
T
i
,
k
=
T
i
,
k
-
T
i
,
k
-
1
,
i
∈
{
1
,
4
}
,
Δ
C
[
T
j
,
k
κ
-
1
]
=
C
[
T
j
,
k
κ
-
1
]
-
C
[
T
j
,
k
-
1
κ
-
1
]
,
j
∈
{
2
,
3
}
,
Γ
k
=
[
Δ
T
1
,
k
Δ
T
4
,
k
]
T
,
Ξ
k
=
[
Δ
C
[
T
2
,
k
κ
-
1
]
Δ
C
[
T
3
,
k
κ
-
1
]
]
T
·
ψ
k
=
ψ
k
-
1
+
[
11
]
Γ
k
+
f
o
f
c
,
k
[
-
1
-
1
]
Ξ
k
.
(
16
)
9. The clock synchronization apparatus according to claim 8 , wherein the controller defines errors of the estimation of the packet delay of the first packet and the packet delay of the second packet by the following Equations (17) and (18);
ɛ
δ
,
k
=
1
2
f
0
{
(
f
c
,
k
-
f
0
)
(
T
4
,
k
-
T
1
,
k
)
-
f
c
,
k
ψ
k
}
(
17
)
ɛ
ϕ
,
k
=
1
2
f
0
{
f
c
,
k
ψ
k
-
(
f
c
,
k
-
f
0
)
(
T
4
,
k
-
T
1
,
k
)
}
(
18
)
models the clock offset {circumflex over (δ)} k new and the packet delay {circumflex over ({circumflex over (ϕ)})} s,k new considering the errors by the following Equations (19) and (20), respectively, n k refers to relative noise with respect to the clock of the slave node; and
δ
^
k
new
=
δ
^
k
1588
-
ɛ
δ
,
k
+
n
k
(
19
)
ϕ
^
s
,
k
new
=
f
0
f
c
,
k
(
ϕ
^
s
,
k
1588
-
ɛ
ϕ
,
k
+
n
k
)
,
where
δ
^
k
1588
=
(
C
[
T
2
,
k
κ
-
1
]
-
T
1
,
k
)
-
ϕ
^
s
,
k
1588
and
ϕ
^
s
,
k
1588
=
1
2
{
(
T
4
,
k
-
C
[
T
3
,
k
κ
-
1
]
)
+
(
C
[
T
2
,
k
κ
-
1
]
-
T
1
,
k
)
}
,
(
20
)
estimates the clock offset and the packet delay by inputting the time information to the modeled clock offset {circumflex over (δ)} k new and the packet delay {circumflex over (ϕ)} s,k new .
10. The clock synchronization apparatus according to claim 6 , further comprising an output unit to output the estimated clock offset and the packet delay to the slave node so that the slave node modifies the clock of the slave node based on the estimated clock offset and the packet delay.