Method for controlling backlight source based on synchronous signal compensation and liquid crystal display

1. A method for controlling a backlight source, comprising:

determining N time intervals of N+1 pulses of a synchronous signal outputted by an image processing chip,

wherein N is a positive integer;

determining an adjustment factor according to the N time intervals of the N+1 pulses of the synchronous signal and a preset adjustment formula;

determining an output delay compensation value of the synchronous signal, according to the adjustment factor, fixed response delay time for processing the synchronous signal and a preset compensation value determination formula;

generating a compensated synchronous signal according to the output delay compensation value of the synchronous signal; and

transmitting the compensated synchronous signal to a pulse width modulation (PWM) driver.

2. The method according to claim 1 , wherein before the determining N time intervals of N+1 pulses of a synchronous signal outputted by an image processing chip, the method also comprises:

receiving the synchronous signal and partition backlight data outputted by the image processing chip.

3. The method according to claim 1 , wherein the determining an adjustment factor according to the N time intervals of the N+1 pulses of the synchronous signal and a preset adjustment formula, comprises:

determining an adjustment factor T c =(Σ N-M T t )/M−T c according to the N time intervals T i of the N+1 pulses of the synchronous signal; the determining an output delay compensation value of the synchronous signal, according to the adjustment factor, fixed response delay time for processing the synchronous signal and a preset compensation value determination formula, comprises:

determining an output delay compensation value T o =(T o +T e )/x of the synchronous signal, according to the adjustment factor T c and fixed response delay time T o for processing the synchronous signal, wherein x is a frequency multiplication number for performing frequency multiplication processing on the synchronous signal;

wherein i €[1, N],M, I, x are positive integers.

4. The method according to claim 3 , wherein x is a positive integer greater than or equal to 2;

before the determining an adjustment factor according to the N time intervals of the N+1 pulses of the synchronous signal and a preset adjustment formula, the method also comprises:

determining an output cycle of the synchronous signal according to the N time intervals of the N+1 pulses of the synchronous signal;

the generating a compensated synchronous signal according to the output delay compensation value of the synchronous signal, comprises:

adjusting a cycle of the synchronous signal according to the output cycle of the synchronous signal, and generating a compensated synchronous signal by applying the output delay compensation value of the synchronous signal to a synchronous signal with an adjusted cycle.

5. The method according to claim 4 , wherein the determining an output cycle of the synchronous signal, according to the N time intervals of the N+1 pulses of the synchronous signal, comprises:

determining an output cycle T=T N /x of the synchronous signal,

according to a last time interval T N in the N time intervals of the N+1 pulses of the synchronous signal and the frequency multiplication number x for performing frequency multiplication processing on the synchronous signal.

6. The method according to claim 4 , wherein the determining an output cycle of the synchronous signal according to the N time intervals of the N+1 pulses of the synchronous signal, comprises:

determining an output cycle T′=(Σ N-M T i )/(M×x) of the synchronous signal, according to last M time intervals in the N time intervals of the N+1 pulses of the synchronous signal and the frequency multiplication number x for performing frequency multiplication processing on the synchronous signal.

7. The method according to claim 1 , wherein the transmitting the compensated synchronous signal to a PWM driver, comprises:

generating duty cycle data and backlight current data according to the compensated synchronous signal and received partition backlight data, and transmitting the duty cycle data, the backlight current data and the compensated synchronous signal to the PWM driver.

8. A liquid crystal display, comprising a processor and a non-transitory processor-readable medium including computer-executable instructions executed by the computing hardware to perform, on the liquid crystal display, operations comprising:

determining time intervals of a synchronous signal;

determining an output delay compensation value of the synchronous signal, according to the time intervals and fixed response delay time for processing the synchronous signal; and

generating a compensated synchronous signal according to the output delay compensation value of the synchronous signal; and transmitting the compensated synchronous signal to a pulse width modulation (PWM) driver,

wherein the operation of determining time intervals of a synchronous signal comprises:

determining N time intervals of N+1 pulses of the synchronous signal outputted by an image processing chip, wherein N is a positive integer;

wherein the operation of determining an output delay compensation value of the synchronous signal, according to the time intervals and fixed response delay time for processing the synchronous signal comprises:

determining an adjustment factor according to the N time intervals of the N+1 pulses of the synchronous signal and a preset adjustment formula; and

determining an output delay compensation value of the synchronous signal according to the adjustment factor, the fixed response delay time for processing the synchronous signal and a preset compensation value determination formula.

9. The liquid crystal display according to claim 8 , wherein before the determining time intervals of a synchronous signal, the operations further comprise:

receiving the synchronous signal and partition backlight data outputted by the image processing chip.

10. The liquid crystal display according to claim 8 , wherein the operations further comprise:

determine the adjustment factor T c =(Σ N-M T i )/M−T N according to the N time intervals T i of the N+1 pulses of the synchronous signal;

determining the output delay compensation value T o =(T o +T c )/x of the synchronous signal, according to the adjustment factor T c , and the fixed response delay time T o for processing the synchronous signal, wherein x is a frequency multiplication number for performing frequency multiplication processing on the synchronous signal;

wherein i€[1, N],M, I, x are positive integers.

11. The liquid crystal display according to claim 10 , wherein, x is a positive integer greater than or equal to 2;

the operations further comprise:

determining an output cycle of the synchronous signal according to the N time intervals of the N+1 pulses of the synchronous signal before determining the output delay compensation value of the synchronous signal; and

adjusting a cycle of the synchronous signal according to the output cycle of the synchronous signal, and generating a compensated synchronous signal by applying the output delay compensation value of the synchronous signal to a synchronous signal with an adjusted cycle; generating duty cycle data and backlight current data according to the compensated synchronous signal and partition backlight data, and transmitting the duty cycle data, the backlight current data and the compensated synchronous signal to the PWM driver.

12. The liquid crystal display according to claim 11 , wherein the operations further comprise:

determining the output cycle T′=T N /x of the synchronous signal, according to a last time interval T N in the N time intervals of the N+1 pulses of the synchronous signal and a frequency multiplication number x for performing frequency multiplication processing on the synchronous signal.

13. The liquid crystal display according to claim 11 , wherein the operations further comprise:

determining the output cycle T′=(Σ N-M T i )/(M×x) of the synchronous signal, according to last M time intervals in the N time intervals of the N+1 pulses of the synchronous signal and a frequency multiplication number x for performing frequency multiplication processing on the synchronous signal.

14. The liquid crystal display, comprising:

an image processing chip, a backlight processor, a pulse width modulation (PWM) driver, a backlight source;

the backlight processor is connected between the image processing chip and the PWM driver, and the PWM driver is connected between the backlight processor and the backlight source;

the image processing chip is configured to conduct image processing to inputted video signals and generate a synchronous signal and partition backlight data;

the backlight processor is configured to:

receive the synchronous signal and the partition backlight data;

detect N time intervals among N+1 pulses of the received synchronous signal;

determine an adjustment factor according to the N time intervals of the N+1 pulses of the synchronous signal and a preset adjustment formula;

determine an output delay compensation value of the synchronous signal, according to the adjustment factor, fixed response delay time for processing the synchronous signal and a preset compensation value determination formula;

generate a compensated synchronous signal according to the output delay compensation value of the synchronous signal and the synchronous signal; and

output the partition backlight data and the compensated synchronous signal,

the PWM driver is configured to receive the partition backlight data and the compensated synchronous signal outputted by the backlight processor; and generate control signals according to the partition backlight data and the compensated synchronous signal; and

the backlight source is configured to receive the control signals and be lit up according to the received control signals.

15. The liquid crystal display according to claim 14 , wherein the backlight processor is configured to apply the output delay compensation value of the synchronous signal to an (N+2)th pulse of the synchronous signal to generate the compensated synchronous signal.

16. The liquid crystal display according to claim 14 , wherein values of the time delays of the P paths of the control signals form an arithmetic progression.