Memory device for performing internal process and operating method thereof
A memory device includes a memory cell array having a plurality of memory cell groups with a corresponding plurality of independent channels, and the device and an operating method thereof perform an internal data processing operation for the memory cell groups. The memory device includes an internal command generator configured to generate one or more internal commands in order to perform an internal data processing operation in response to a reception of a command, and an internal common bus for a common internal processing channel which is disposed to be shared by the plurality of memory cell groups and configured to form a transmission path of data between the plurality of memory cell groups when the internal data processing operation is performed.
1. A memory device comprising:
a buffer die including an internal command generator configured to serially generate internal commands so that an internal process corresponding to a command received from the outside is performed;
a first through N core dies including separate channels configured to communicate in accordance with independent interfaces (N is integer greater than 1), each of the first through N core dies further including a processor in memory (PIM) performing a processing operation with respect to data; and
an internal common bus disposed to be shared by the channels and configured to form a transmission path of data between the channels when the internal process is performed,
wherein, the PIM performs the processing operation using at least one of read data read from the memory device and write data provided to the memory device.
2. The memory device of claim 1 , wherein, during the internal process, date from one core die is delivered to one or more other core dies through the internal common bus.
3. The memory device of claim 1 , wherein the first core die includes a first command decoder configured to decode the internal commands and generate internal control signals,
wherein the date from the first core die is delivered to the second core die through the internal common bus based on the control of the first command decoder.
4. The memory device of claim 1 , wherein the internal command generator includes an in-memory processor.
5. The memory device of claim 1 , further comprising:
a plurality of through-silicon vias (TSVs) formed to pass through the first through N core dies,
wherein at least some of the plurality of TSVs are used as the internal common bus when the internal process is performed.
6. The memory device of claim 1 , wherein the each of the first through N core dies processes a plurality of data in parallel and includes a plurality of PIMs corresponding to the plurality of data.
7. The memory device of claim 1 , wherein the each of the first through N core dies includes a command decoder controlling an internal operation by decoding internal commands from the buffer die, and
wherein the PIM is controlled by a PIM control signal according to a decoding result of the internal commands.
8. The memory device of claim 1 , wherein the PIM includes a function circuit performing a Boolean function, and
wherein the function circuit perform at least one of AND, OR, XOR and NOT functions with respect to at least one of the read data and the write data.
9. A memory device comprising:
a buffer die including an internal command generator configured to serially generate internal commands so that an internal process corresponding to a command received from the outside is performed;
a first through N core dies including separate channels configured to communicate in accordance with independent interfaces (N is integer greater than 1), each of the first through N core dies including a processor in memory (PIM) performing a processing operation with respect to data; and
an internal common bus disposed to be shared by the channels and configured to form a transmission path of data between the channels when the internal process is performed,
wherein the internal process includes an RMW (Read Modify Write) operation for writing write data in a cell core of the first core die in an RMW method, and
wherein the first core die includes a first PIM configured to perform calculation processing for the write data and read data read from the cell core of the first core die.
10. The memory device of claim 9 , wherein the first PIM performs a comparison operation for the write data and the read data, and
wherein, based on a result of the comparison operation, only some bits of the write data are selectively written in the cell core of the first core die.
11. The memory device of claim 9 , wherein the write data is provided to the first PIM through the internal common bus.
12. The memory device of claim 9 , wherein the internal command generator includes an in-memory processor, and
wherein, during the RMW operation, the in-memory processor generates a chip selection signal for selection of the first core die.
13. The memory device of claim 9 , wherein the first PIM includes a first latch for storing the read data, a function unit for performing a comparison operation for the write data and the read data, and a second latch for storing a result of the comparison operation.
14. The memory device of claim 13 , wherein the first PIM further includes a first switch disposed between the first latch and the internal common bus and a second switch disposed between the function unit and the internal common bus,
wherein the read data is provided to the first latch when the first switch is turned on, and the write data is provided to the function unit when the second switch is turned on.
15. A memory device comprising:
a buffer die including an internal command generator configured to serially generate internal commands so that an internal process corresponding to a command received from the outside is performed;
a first through N core dies including separate channels configured to communicate in accordance with independent interfaces (N is integer greater than 1), each of the first through N core dies including a processor in memory (PIM) performing a processing operation with respect to data; and
an internal common bus disposed to be shared by the channels and configured to form a transmission path of data between the channels when the internal process is performed,
wherein the internal process includes a mask write operation in which data is mask-written in a first cell core of the first core die,
wherein the first core die includes a first PIM and the second core die includes a second PIM, and
wherein each of the first PIM and the second PIM controls data to be provided to the first cell core based on a bit value of mask data.
16. The memory device of claim 15 , wherein, during the mask write operation, read data read from the first core die is provided to the first PIM, write data is provided to the second PIM, and the mask data is commonly provided to the first PIM and the second PIM, and
data stored in the first PIM or the second PIM, bit by bit, is selectively written in the first cell core according to the bit value of the mask data.
17. The memory device of claim 16 , wherein the mask data is commonly provided to the first PIM and the second PIM through the internal common bus.
18. The memory device of claim 16 , wherein the first PIM includes a first latch for storing the read data, a second latch for storing the mask data, and a first buffer controlling an output of the read data according to the bit value of the mask data, and
wherein the second PIM includes a third latch for storing the write data, a fourth latch for storing the mask data, and a second buffer controlling an output of the write data according to the bit value of the mask data.
19. The memory device of claim 18 , wherein the fourth latch stores an inverted bit value of the mask data, and
data from any one of the first buffer and the second buffer is selectively provided to the first cell core according to the bit value of the mask data in the second latch and the inverted bit value of the mask data in the fourth latch.
20. The memory device of claim 18 , wherein the first PIM further includes a first switch disposed between the first latch and the internal common bus and a second switch disposed between the second latch and the internal common bus, and
wherein the second PIM further includes a third switch disposed between the third latch and the internal common bus and a fourth switch disposed between the fourth latch and the internal common bus.