Semiconductor devices and methods of manufacturing the same
A semiconductor device includes a gate structure extending in a second direction on a substrate, a source/drain layer disposed on a portion of the substrate adjacent the gate structure in a first direction crossing the second direction, a first conductive contact plug on the gate structure, and a second contact plug structure disposed on the source/drain layer. The second contact plug structure includes a second conductive contact plug and an insulation pattern, and the second conductive contact plug and the insulation pattern are disposed in the second direction and contact each other. The first conductive contact plug and the insulation pattern are adjacent to each other in the first direction. The first and second conductive contact plugs are spaced apart from each other.
1. A semiconductor device comprising:
a substrate;
an isolation pattern disposed on the substrate;
a plurality of active regions disposed on the substrate and defined by the isolation pattern, each of the plurality of active regions being spaced apart from each other;
a gate structure disposed on the plurality of active regions, the gate structure extending in the first direction;
a source/drain disposed on the plurality of active regions;
a first contact plug disposed on the gate structure; and
a second contact plug disposed on the source/drain and spaced apart from the first contact plug,
wherein the first and second contact plugs are not aligned with each other in a second direction substantially perpendicular to the first direction.
2. The semiconductor device of claim 1 , wherein the first contact plug vertically overlaps a first one of the plurality of active regions.
3. The semiconductor device of claim 1 , wherein the second contact plug vertically overlaps a second one of the plurality of active regions.
4. The semiconductor device of claim 1 , further comprising a metal silicide disposed on the source/drain and contacting the second contact plug.
5. The semiconductor device of claim 1 , wherein a bottom surface of the second contact plug has a shape corresponding to a shape of a top surface of the source/drain.
6. The semiconductor device of claim 1 , further comprising a gate spacer disposed on sidewalls of the gate structure.
7. The semiconductor device of claim 1 , wherein a lower portion of each of the plurality of active regions is covered by the isolation pattern.
8. The semiconductor device of claim 1 , wherein the isolation pattern comprises silicon oxide and the gate insulation pattern comprises metal oxide.
9. A semiconductor device comprising:
a substrate;
an isolation pattern disposed on the substrate;
a plurality of active fins disposed on the substrate and defined by the isolation pattern, each of the plurality of active fins being spaced apart from each other;
a gate structure disposed on the plurality of active fins;
a first source/drain disposed on the plurality of active fins;
a first contact plug disposed on the gate structure;
a second contact plug disposed on the first source/drain and spaced apart from the first contact plug; and
a metal silicide disposed on the first source/drain and contacting the second contact plug,
wherein a bottom surface of the second contact plug has a shape corresponding to a shape of a top surface of the first source/drain, and
wherein the bottom surface of the second contact plug is uneven.
10. The semiconductor device of claim 9 , wherein the first contact plug vertically overlaps a first one of the plurality of active fins, and the second contact plug vertically overlaps a second one of the plurality of active fins.
11. The semiconductor device of claim 9 , further comprising a gate spacer disposed on sidewalls of the gate structure.
12. The semiconductor device of claim 9 , wherein a lower portion of each of the plurality of active fins is covered by the isolation pattern.
13. The semiconductor device of claim 9 , further comprising a second source/drain disposed on the plurality of active fins and contacting the first source/drain.
14. The semiconductor device of claim 9 , further comprising a fin spacer disposed on sidewalls of the plurality of active fins.
15. A semiconductor device comprising:
a substrate;
an isolation pattern disposed on the substrate;
a plurality of active regions disposed on the substrate and defined by the isolation pattern, each of the plurality of active regions being spaced apart from each other;
a gate structure disposed on the plurality of active regions;
a first source/drain disposed on the plurality of active regions;
a first contact plug disposed on the gate structure;
a second contact plug disposed on the first source/drain and spaced apart from the first contact plug; and
a metal silicide disposed on the first source/drain and contacting the second contact plug,
wherein the first contact plug vertically overlaps a first one of the plurality of active regions, and
the second contact plug vertically overlaps a second one of the plurality of active regions.
16. The semiconductor device of claim 15 , wherein a bottom surface of the second contact plug has a shape corresponding to a shape of a top surface of the first source/drain.
17. The semiconductor device of claim 15 , wherein the top surface of the first source/drain is uneven.
18. The semiconductor device of claim 15 , further comprising a gate spacer disposed on sidewalls of the gate structure.
19. The semiconductor device of claim 15 , wherein a lower portion of each of the plurality of active regions is covered by the isolation pattern.
20. The semiconductor device of claim 15 , further comprising a second source/drain disposed on the plurality of active fins and contacting the first source/drain.