IP Library › Granted Patent US 10,410,924
Granted Patent B2
US 10,410,924 · App. 15/860,827 · Granted Sep 10, 2019

Manufacturing process of element chip

Inventors: Hidehiko Karasaki (Osaka, JP); Hidefumi Saeki (Osaka, JP); Atsushi Harikai (Osaka, JP)
Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
H01L21/78B23K26/062B23K26/359H01L21/02076H01L21/268H01L21/3065H01L21/67103H01L21/67109H01L21/6831H01L21/82H01L23/544B23K2103/56H01J37/321H01J2237/334H01L2223/5446
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,410,924
App. No.
15/860,827
Granted
Sep 10, 2019
Kind
B2
Abstract

Provided is a manufacturing process of an element chip, which comprises a preparation step for preparing a substrate including a semiconductor layer having first and second sides and a wiring layer on the first side thereof, the substrate having a plurality of dicing regions and element regions defined by the dicing regions, a scribing step for radiating a laser beam towards the first side of the wiring layer onto the dicing regions to form apertures exposing the semiconductor layer along the dicing regions, and a dicing step for dicing the substrate along the apertures into a plurality of the element chips, wherein the laser beam has a beam profile having a M-shaped distribution whose peripheral intensity is greater than a central intensity in a width direction of the laser beam along the dicing regions.

Claims (11)

1. A manufacturing process of an element chip, comprising:

a preparation step for preparing a substrate including a semiconductor layer having first and second sides and a wiring layer on the first side thereof, the substrate having a plurality of dicing regions and element regions defined by the dicing regions;

a scribing step for radiating a laser beam towards the first side of the wiring layer onto the dicing regions to form apertures exposing the semiconductor layer along the dicing regions; and

a dicing step for dicing the substrate along the apertures into a plurality of the element chips,

wherein the laser beam has a beam profile having a single M-shaped distribution extending over a whole width of the dicing regions, whose peripheral intensity is greater than a central intensity in a width direction of the laser beam along the dicing regions.

2. The manufacturing process according to claim 1 , wherein the semiconductor layer exposed by the apertures is etched by a first plasma exposure in the dicing step.

3. The manufacturing process according to claim 1 , wherein a spot shape of the laser beam is oval, elliptical or similar thereto, of which outline has a minor diameter corresponding to the width of the dicing regions.

4. The manufacturing process according to claim 1 , wherein a spot shape of the laser beam is a rectangular shape having a member extending along a direction of a width of the dicing regions, or a shape similar thereto.

5. The manufacturing process according to claim 1 , wherein a beam profile of the laser beam has a distribution selected from a group consisting of a Gaussian distribution and a top hat distribution along a longitudinal direction of the laser beam.

6. The manufacturing process according to claim 1 , wherein the laser beam is radiated two or more times to form the apertures in the dicing regions during the scribing step.

7. The manufacturing process according to claim 1 , further comprising a cleaning step for cleaning the apertures by a second plasma exposure after the scribing step, wherein the dicing step is implemented after the cleaning step.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 2, 2018
From: KARASAKI, HIDEHIKO; SAEKI, HIDEFUMI; HARIKAI, ATSUSHI
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 045086/0476 →
Priority Claims (2)
JP 2017-003671 · Jan 12, 2017 · national
JP 2017-021468 · Feb 8, 2017 · national
Continuity (1)
Related Publication 20180197777A1 · Jul 12, 2018
Cited By (1)
US 12,230,484