IP Library Granted Patent US 10,410,976
Granted Patent B2
US 10,410,976 · App. 15/240,625 · Granted Sep 10, 2019

Method of manufacturing semiconductor chip, semiconductor chip, and semiconductor device

Inventors: Yusaku Asano (Yokohama, JP); Kazuhito Higuchi (Yokohama, JP); Taizo Tomioka (Yokohama, JP); Tomohiro Iguchi (Kawasaki, JP)
Assignee: KABUSHIKI KAISHA TOSHIBA
H01L23/562H01L21/308H01L21/3081H01L21/30604H01L21/78H01L23/3121H01L23/3192H01L23/544H01L2223/5448H01L2224/32245H01L2224/48091H01L2224/48247H01L2224/73265H01L2924/181
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Quick Facts
Patent No.
US 10,410,976
App. No.
15/240,625
Granted
Sep 10, 2019
Kind
B2
Abstract

A method of manufacturing a semiconductor chip according to an embodiment includes forming on a semiconductor substrate a plurality of etching masks each including a protection film to demarcate a plurality of first regions of the substrate protected by the plurality of etching masks and a second region as an exposed region of the substrate, and anisotropically removing the second region by a chemical etching process to form a plurality of grooves each including a side wall at least partially located in the same plane as an end face of the etching mask and a bottom portion reaching a back surface of the substrate, thereby singulating the semiconductor substrate into a plurality of chip main bodies corresponding to the plurality of first regions.

Claims (13)

1. A semiconductor chip comprising:

a chip main body including a surface region which includes a semiconductor element,

wherein an end face of the chip main body has stripe-shaped recesses or projections, each of the recesses extending from a surface of the chip main body on the surface region's side toward an opposite surface thereof and each of the projections each extending from a surface of the chip main body on the surface region's side toward an opposite surface thereof, and

each of the recesses or the projections has a width of 10 to 100 nm.

2. The semiconductor chip of claim 1 , further comprising a protection film covering the surface region,

wherein a contour of a surface of the chip main body on the surface region's side agrees, at least partly, with a contour of an orthogonal projection of the protection film onto a plane including the surface of the chip main body on the surface region's side.

3. The semiconductor chip of claim 1 , wherein a surface of the chip main body on the surface region's side includes no corner portion which is defined by two line segments which are in contact at one end.

4. The semiconductor chip of claim 1 , wherein the semiconductor element includes a transistor.

5. The semiconductor chip of claim 1 , wherein the semiconductor element includes a diode.

6. The semiconductor chip of claim 1 , wherein the semiconductor element includes a light-emitting diode.

7. The semiconductor chip of claim 1 , wherein the semiconductor element includes a semiconductor laser.

8. The semiconductor chip of claim 4 , wherein the element region further includes a capacitor.

9. The semiconductor chip of claim 4 , wherein the element region further includes a wiring.

Priority Claims (2)
JP 2013-235470 · Nov 13, 2013 · national
JP 2014-218512 · Oct 27, 2014 · national
Continuity (2)
Division 14540360 · Nov 13, 2014
Related Publication 20160358863A1 · Dec 8, 2016
Cited By (8)
US 12,266,640 US 12,266,650 US 12,272,677 US 12,341,025 US 12,347,820 US 12,401,011 US 12,406,959 US 12,564,084