IP Library › Granted Patent US 10,410,986
Granted Patent B2
US 10,410,986 · App. 15/980,033 · Granted Sep 10, 2019

Semiconductor device and manufacture thereof

Inventors: You Wu (Shanghai, CN); Jun Zhu (Shanghai, CN)
Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION; SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
H01L24/05H01L24/03H01L27/1464H01L27/14632H01L27/14687H01L2224/0345H01L2224/03614H01L2224/03622H01L2224/04042H01L2224/05018H01L2224/05027H01L2224/05124
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,410,986
App. No.
15/980,033
Granted
Sep 10, 2019
Kind
B2
Abstract

A semiconductor device and its manufacturing method are presented. The manufacturing method includes: providing a semiconductor structure comprising: an interlayer dielectric layer, a first metal layer surrounded by the interlayer dielectric layer, and a semiconductor layer on the interlayer dielectric layer; etching the semiconductor layer to form an opening exposing the interlayer dielectric layer, wherein the opening comprises a first opening and a second opening on the first opening; forming an insulation layer on the semiconductor structure; etching the insulation layer and the interlayer dielectric layer at the bottom of the first opening to form a groove exposing a portion of the first metal layer; forming a second metal layer on the insulation layer and on the bottom and a side surface of the groove; and patterning the second metal layer. The second metal layer in this inventive concept can be removed more completely than conventional methods.

Claims (11)

1. A semiconductor device, comprising:

an interlayer dielectric layer;

a first metal layer surrounded by the interlayer dielectric layer, wherein the interlayer dielectric layer comprises a groove exposing a portion of the first metal layer;

a semiconductor layer on the interlayer dielectric layer, wherein the semiconductor layer comprises an opening exposing the interlayer dielectric layer, and wherein the opening comprises a first opening and a second opening on the first opening, with the first opening exposing a portion of the interlayer dielectric layer, and the first opening and the second opening forming a staircase pattern;

an insulation layer on the semiconductor layer, on the bottom and a side surface of the opening, and on the staircase pattern; and

a patterned second metal layer on the insulation layer and on the bottom and a side surface of the groove, with the second metal layer contacting the first metal layer, wherein the insulation layer comprises a first side, a second side, and a third side, wherein the first side is completely positioned inside the second opening and is connected through the second side to the third side, wherein the second side is oblique relative to each of the first side and the third side, wherein the third side directly contacts the second metal layer, and wherein both the first side and the second side are completely exposed by the second metal layer between two opposite portions of the second metal layer.

2. The device of claim 1 , wherein the width of the second opening is larger than the width of the first opening.

3. The device of claim 1 , wherein an angle between a side surface of the first opening and the bottom of the first opening is an obtuse angle, and an angle between a side surface of the second opening and a flat surface of the staircase pattern is an obtuse angle.

4. The device of claim 1 , wherein an angle between a side surface of the first opening and the bottom of the first opening is in a range of 100° to 110°, and an angle between a side surface of the second opening and a flat surface of the staircase pattern is in a range of 100° to 110°.

5. The device of claim 1 , wherein the interlayer dielectric layer comprises silicon dioxide, the semiconductor layer comprises silicon, the first metal layer comprises aluminum, the insulation layer comprises silicon dioxide, and the second metal layer comprises aluminum.

6. The device of claim 1 , wherein the second metal layer directly contacts a face of the first metal layer, and wherein the first side of the insulation layer is parallel to the face of the first metal layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 15, 2018
From: WU, YOU; ZHU, JUN
To: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION; SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
Reel/Frame 045808/0614 →
Priority Claims (1)
CN 2017 1 0350090 · May 18, 2017 · national
Continuity (1)
Related Publication 20180337150A1 · Nov 22, 2018