Semiconductor device and memory device
View Patent ↗To provide a semiconductor device with large storage capacity and low power consumption. The semiconductor device includes an oxide semiconductor, a first transistor, a second transistor, and a dummy word line. A channel formation region in the first transistor and a channel formation region in the second transistor are formed in different regions in the oxide semiconductor. The dummy word line is provided to extend between the channel formation region in the first transistor and the channel formation region in the second transistor. By applying a predetermined potential to the dummy word line, the first transistor and the second transistor are electrically isolated in a region of the oxide semiconductor which intersects the dummy word line.
1. A semiconductor device comprising:
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a first capacitor;
a second capacitor;
a first wiring;
a second wiring; and
a third wiring,
wherein the first wiring serves as a gate of the first transistor and a gate of the third transistor,
wherein a first terminal of the first capacitor is electrically connected to one of a source electrode and a drain electrode of the first transistor,
wherein the second wiring serves as a gate of the second transistor and a gate of the fourth transistor,
wherein a first terminal of the second capacitor is electrically connected to one of a source electrode and a drain electrode of the second transistor,
wherein a channel formation region in the first transistor is formed in a first oxide semiconductor,
wherein a channel formation region in the second transistor is formed in the first oxide semiconductor,
wherein a channel formation region in the third transistor is formed in a second oxide semiconductor,
wherein a channel formation region in the fourth transistor is formed in the second oxide semiconductor,
wherein the first oxide semiconductor and the second oxide semiconductor are separated from each other,
wherein the third wiring is between the first transistor and the second transistor,
wherein the third wiring is between the third transistor and the fourth transistor,
wherein the first wiring, the second wiring and the third wiring are formed from a same conductive film,
wherein the third wiring overlaps with the first oxide semiconductor with an insulating film interposed therebetween,
wherein the first transistor and the second transistor are configured to be electrically isolated by a potential of the third wiring, and
wherein the third transistor and the fourth transistor are configured to be electrically isolated by the potential of the third wiring.
2. The semiconductor device according to claim 1 , further comprising:
a fourth wiring; and
a fifth wiring,
wherein the fourth wiring is electrically connected to the other of the source electrode and the drain electrode of the first transistor,
wherein the fifth wiring is electrically connected to the other of the source electrode and the drain electrode of the second transistor,
wherein the first oxide semiconductor overlaps with the first wiring, the second wiring, the third wiring, the fourth wiring, and with the fifth wiring,
wherein the fourth wiring overlaps with the first wiring, the second wiring, and the third wiring, and
wherein the fifth wiring overlaps with the first wiring, the second wiring, and the third wiring.
3. The semiconductor device according to claim 1 , further comprising a sixth wiring,
wherein the sixth wiring is provided to overlap with the third wiring with the first oxide semiconductor and the second oxide semiconductor positioned between the sixth wiring and the third wiring,
wherein the first transistor and the second transistor are configured to be electrically isolated by a potential of the sixth wiring, and
wherein the third transistor and the fourth transistor are configured to be electrically isolated by a potential of the sixth wiring.
4. The semiconductor device according to claim 1 , further comprising:
a seventh wiring; and
an eighth wiring,
wherein the seventh wiring serves as a back gate of the first transistor and a back gate of the third transistor,
wherein the seventh wiring is provided to overlap with the first wiring with the channel formation region in the first transistor positioned between the seventh wiring and the first wiring,
wherein the eighth wiring serves as a back gate of the second transistor and a back gate of the fourth transistor, and
wherein the eighth wiring is provided to overlap with the second wiring with the channel formation region in the second transistor positioned between the eighth wiring and the second wiring.
5. The semiconductor device according to claim 1 ,
wherein the first oxide semiconductor comprises at least one of indium, an element M, and zinc, and
wherein the element M represents any one of aluminum, gallium, yttrium, and tin.
6. An electronic device comprising:
the semiconductor device according to claim 1 ; and
a housing,
wherein the semiconductor device is provided in the housing.
7. A semiconductor device comprising:
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor;
a sixth transistor;
a first capacitor;
a second capacitor;
a first wiring;
a second wiring; and
a third wiring,
wherein the first wiring serves as a gate of the first transistor and a gate of the fifth transistor,
wherein a first terminal of the first capacitor is electrically connected to one of a source electrode and a drain electrode of the first transistor,
wherein a gate of the second transistor is electrically connected to one of the source electrode and the drain electrode of the first transistor,
wherein the second wiring serves as a gate of the third transistor and a gate of the sixth transistor,
wherein a first terminal of the second capacitor is electrically connected to one of a source electrode and a drain electrode of the third transistor,
wherein a gate of the fourth transistor is electrically connected to one of the source electrode and the drain electrode of the third transistor,
wherein a channel formation region in the first transistor is formed in a first oxide semiconductor,
wherein a channel formation region in the third transistor is formed in the first oxide semiconductor,
wherein a channel formation region in the fifth transistor is formed in a second oxide semiconductor,
wherein a channel formation region in the sixth transistor is formed in the second oxide semiconductor,
wherein the first oxide semiconductor and the second oxide semiconductor are separated from each other,
wherein the third wiring is between the first transistor and the second transistor,
wherein the third wiring is between the fifth transistor and the sixth transistor,
wherein the first wiring, the second wiring and the third wiring are formed from a same conductive film,
wherein the third wiring overlaps with the first oxide semiconductor with an insulating film interposed therebetween,
wherein the first transistor and the second transistor are configured to be electrically isolated by a potential of the third wiring, and
wherein the fifth transistor and the sixth transistor are configured to be electrically isolated by the potential of the third wiring.
8. The semiconductor device according to claim 7 , further comprising:
a fourth wiring;
a fifth wiring;
a sixth wiring;
a seventh wiring; and
an eighth wiring,
wherein the fourth wiring is electrically connected to the other of the source electrode and the drain electrode of the first transistor,
wherein the fifth wiring is electrically connected to one of a source electrode and a drain electrode of the second transistor,
wherein the sixth wiring is electrically connected to the other of the source electrode and the drain electrode of the third transistor,
wherein the seventh wiring is electrically connected to one of a source electrode and a drain electrode of the fourth transistor,
wherein the eighth wiring is electrically connected to the other of the source electrode and the drain electrode of the second transistor,
wherein the eighth wiring is electrically connected to the other of the source electrode and the drain electrode of the fourth transistor,
wherein the first oxide semiconductor overlaps with the first wiring, the second wiring, the third wiring, the fourth wiring, the fifth wiring, the sixth wiring, the seventh wiring, and the eighth wiring,
wherein the first wiring overlaps with the fourth wiring, the fifth wiring, the sixth wiring, the seventh wiring, and the eighth wiring,
wherein the second wiring overlaps with the fourth wiring, the fifth wiring, the sixth wiring, the seventh wiring, and the eighth wiring, and
wherein the third wiring overlaps with the fourth wiring, the fifth wiring, the sixth wiring, the seventh wiring, and the eighth wiring.
9. The semiconductor device according to claim 7 , further comprising:
a fourth wiring;
a fifth wiring; and
a sixth wiring,
wherein the fourth wiring is electrically connected to the other of the source electrode and the drain electrode of the first transistor,
wherein the fourth wiring is electrically connected to one of a source electrode and a drain electrode of the second transistor,
wherein the fifth wiring is electrically connected to the other of the source electrode and the drain electrode of the third transistor,
wherein the fifth wiring is electrically connected to one of a source electrode and a drain electrode of the fourth transistor,
wherein the sixth wiring is electrically connected to the other of the source electrode and the drain electrode of the second transistor,
wherein the sixth wiring is electrically connected to the other of the source electrode and the drain electrode of the fourth transistor,
wherein the first oxide semiconductor overlaps with the first wiring, the second wiring, the third wiring, the fourth wiring, the fifth wiring, and the sixth wiring,
wherein the first wiring overlaps with the fourth wiring, the fifth wiring, and the sixth wiring,
wherein the second wiring overlaps with the fourth wiring, the fifth wiring, and the sixth wiring, and
wherein the third wiring overlaps with the fourth wiring, the fifth wiring, and the sixth wiring.
10. The semiconductor device according to claim 7 , further comprising a ninth wiring,
wherein the ninth wiring is provided to overlap with the third wiring with the first oxide semiconductor and the second oxide semiconductor positioned between the ninth wiring and the third wiring,
wherein the first transistor and the second transistor are configured to be electrically isolated by a potential of the ninth wiring, and
wherein the fifth transistor and the sixth transistor are configured to be electrically isolated by a potential of the ninth wiring.
11. The semiconductor device according to claim 7 , further comprising:
a tenth wiring; and
an eleventh wiring,
wherein the tenth wiring serves as a back gate of the first transistor and a back gate of the fifth transistor,
wherein the tenth wiring is provided to overlap with the first wiring with the channel formation region in the first transistor positioned between the tenth wiring and the first wiring,
wherein the eleventh wiring serves as a back gate of the third transistor and a back gate of the sixth transistor, and
wherein the eleventh wiring is provided to overlap with the second wiring with the channel formation region in the third transistor positioned between the eleventh wiring and the second wiring.
12. The semiconductor device according to claim 7 , further comprising an insulating layer,
wherein the first transistor and the third transistor are over the insulating layer, and
wherein the second transistor and the fourth transistor are under the insulating layer.
13. The semiconductor device according to claim 7 ,
wherein at least one of channel formation regions in the second transistor and the fourth transistor comprises silicon.
14. The semiconductor device according to claim 7 ,
wherein the first oxide semiconductor comprises at least one of indium, an element M, and zinc, and
wherein the element M represents any one of aluminum, gallium, yttrium, and tin.
15. An electronic device comprising:
the semiconductor device according to claim 7 ; and
a housing,
wherein the semiconductor device is provided in the housing.
16. The semiconductor device according to claim 1 ,
wherein the gate of the first transistor is over and overlaps with one of the source electrode and the drain electrode of the first transistor,
wherein the gate of the second transistor is over and overlaps with one of the source electrode and the drain electrode of the second transistor,
wherein the third wiring does not overlap with one of the source electrode and the drain electrode of the first transistor and one of the source electrode and the drain electrode of the second transistor.
17. The semiconductor device according to claim 7 ,
wherein the gate of the first transistor is over and overlaps with one of the source electrode and the drain electrode of the first transistor,
wherein the gate of the second transistor is over and overlaps with one of the source electrode and the drain electrode of the second transistor,
wherein the third wiring does not overlap with one of the source electrode and the drain electrode of the first transistor, and one of the source electrode and the drain electrode of the second transistor.