Integrated circuits including magnetic random access memory structures and methods for fabricating the same

1. An integrated circuit comprising a plurality of magnetic random access memory (MRAM) structures, said integrated circuit comprising:

a semiconductor substrate;

a first lower magnetic tunnel junction stack (MTJ stack) overlying said semiconductor substrate;

a second lower MTJ stack spaced from said first lower MTJ stack and overlying said semiconductor substrate;

a dielectric layer disposed between said first lower MTJ stack and said second lower MTJ stack, said dielectric layer overlying said semiconductor substrate;

a spin orbit torque coupling layer overlying said first lower MTJ stack, said dielectric layer, and said second lower MTJ stack;

a first upper MTJ stack overlying said spin orbit torque coupling layer and said first lower MTJ stack; and

a second upper MTJ stack overlying said spin orbit torque coupling layer and said second lower MTJ stack.

2. The integrated circuit of claim 1 , wherein each of the MTJ stacks comprises:

a free layer adjacent said spin orbit torque coupling layer;

a tunnel barrier layer adjacent said free layer and spaced from said spin orbit torque coupling layer; and

a fixed layer adjacent said tunnel barrier layer and spaced from said free layer.

3. The integrated circuit of claim 2 , wherein said free layer of each of said MTJ stacks is configured to switch between a parallel magnetization and an antiparallel magnetization relative to said fixed layer of each of said MTJ stacks in the presence of a first electrical current passing through each of said MTJ stacks.

4. The integrated circuit of claim 2 , wherein:

said free layer of each of said MTJ stacks has a switching energy barrier for switching between a parallel magnetization and an antiparallel magnetization relative to said fixed layer of each of said MTJ stacks;

said spin orbit torque coupling layer is configured to receive a second electrical current, and generate an up polarized current and a down polarized current in response to said second electrical current; and

said down polarized current is configured to induce torque on said free layers of said first lower and said lower second MTJ stacks, and said up polarized current is configured to induce torque on said free layers of said first upper and said second upper MTJ stacks.

5. The integrated circuit of claim 1 , further comprising:

a first pass-gate transistor in electrical communication with said first lower MTJ stack;

a second pass-gate transistor in electrical communication with said first upper MTJ stack; and

a first word line in electrical communication with said first pass-gate transistor and said second pass-gate transistor.

6. The integrated circuit of claim 5 , further comprising a sensing circuit in electrical communication with said spin orbit torque coupling layer, wherein said sensing circuit is configured to determine a difference in resistances of said first lower MTJ stack and said first upper MTJ stack in the presence of a read current.

7. The integrated circuit of claim 1 , further comprising:

a first pass-gate transistor in electrical communication with said first lower MTJ stack;

a first word line in electrical communication with said first pass-gate transistor;

a second pass-gate transistor in electrical communication with said first upper MTJ stack; and

a second word line electrically isolated from said first word line and in electrical communication with said second pass-gate transistor.

8. The integrated circuit of claim 7 , further comprising a sensing circuit in electrical communication with said spin orbit torque coupling layer, wherein said sensing circuit is configured to determine a resistance of said first lower MTJ stack or said first upper MTJ stack in the presence of a read current.

9. The integrated circuit of claim 1 , further comprising:

a first pass-gate transistor in electrical communication with said first lower MTJ stack;

a second pass-gate transistor in electrical communication with said second lower MTJ stack; and

a first word line in electrical communication with said first pass-gate transistor and said second pass-gate transistor.

10. The integrated circuit of claim 1 , further comprising a bottom electrode layer overlying said semiconductor substrate with said first lower MTJ stack and said second lower MTJ stack overlying said bottom electrode layer.

11. The integrated circuit of claim 10 , further comprising a conductive via structure disposed on said bottom electrode layer and in electrical communication with said first lower MTJ stack.

12. The integrated circuit of claim 11 , further comprising a bottom dielectric layer overlying said bottom electrode layer with said conductive via structure extending through said bottom dielectric layer.

13. The integrated circuit of claim 1 , further comprising a contact in electrical communication with said first upper MTJ stack.

14. The integrated circuit of claim 13 , further comprising a top dielectric layer overlying said first upper MTJ stack with said contact extending through said top dielectric layer.

15. The integrated circuit of claim 14 , further comprising a top electrode layer overlying and in electrical communication with said contact and overlying said top dielectric layer.

16. A method for fabricating an integrated circuit comprising a plurality of magnetic random access memory (MRAM) structures, said method comprising:

forming a first lower magnetic tunnel junction stack (MTJ stack) overlying a semiconductor substrate;

forming a second lower MTJ stack spaced from the first lower MTJ stack and overlying the semiconductor substrate;

forming a dielectric layer disposed between the first lower MTJ stack and the second lower MTJ stack, the dielectric layer overlying the semiconductor substrate;

forming a spin orbit torque coupling layer overlying the first lower MTJ stack, the dielectric layer, and the second lower MTJ stack;

a first upper MTJ stack overlying the spin orbit torque coupling layer and the first lower MTJ stack; and

a second upper MTJ stack overlying the spin orbit torque coupling layer and the second lower MTJ stack.

17. The method of claim 16 , further comprising:

forming a first pass-gate transistor in electrical communication with the first lower MTJ stack;

forming a second pass-gate transistor in electrical communication with the first upper MTJ stack; and

forming a first word line in electrical communication with the first pass-gate transistor and the second pass-gate transistor.

18. The method of claim 16 , further comprising:

forming a first pass-gate transistor in electrical communication with the first lower MTJ stack;

forming a first word line in electrical communication with the first pass-gate transistor;

forming a second pass-gate transistor in electrical communication with the first upper MTJ stack; and

forming a second word line electrically isolated from the first word line and in communication with the second pass-gate transistor.

19. The method of claim 16 , further comprising:

forming a first pass-gate transistor in electrical communication with the first lower MTJ stack;

forming a second pass-gate transistor in electrical communication with the second lower MTJ stack; and

forming a first word line in electrical communication with the first pass-gate transistor and the second pass-gate transistor.

20. The method of claim 16 , further comprising forming a sensing circuit in electrical communication with the spin orbit torque coupling layer.