Self-aligned inner-spacer replacement process using implantation
A method for manufacturing a semiconductor device includes forming a stacked configuration of first and second semiconductor layers on a semiconductor substrate, wherein the stacked configuration comprises a repeating arrangement of a second semiconductor layer stacked on a first semiconductor layer, forming a plurality of dummy gates spaced apart from each other on the stacked configuration, wherein the plurality of dummy gates cover a portion of the stacked configuration in a channel region, performing an implantation of a semiconductor material on exposed portions of the stacked configuration in a source/drain region, wherein the implantation increases a concentration of the semiconductor material in the exposed portions of the stacked configuration, and selectively removing first semiconductor layers having an increased concentration of the semiconductor material from the source/drain region, wherein the removed first semiconductor layers correspond in position to the first semiconductor layers in the channel region.
1. A semiconductor device, comprising:
a plurality of nanowires in a region formed in a stacked configuration on a semiconductor substrate, wherein the region is defined by outer edges of a gate structure and outer edges of the plurality of nanowires are aligned with the outer edges of the gate structure;
a plurality of channel extension layers extending from an outer edge of the region, each of the plurality of channel extension layers respectively corresponding to and positioned adjacent a nanowire of the plurality of nanowires in the stacked configuration, wherein each of the plurality of channel extension layers has a higher germanium concentration than its corresponding nanowire;
a first spacer layer formed adjacent the outer edge of the region on each of uppermost channel extension layers of the plurality of extension layers; and
a second spacer layer formed adjacent the outer edge of the region under each channel extension layer and under the first spacer layer;
wherein each of the plurality of channel extension layers comprises silicon germanium, wherein silicon comprises a first concentration and germanium comprises the remaining concentration of each of the plurality of channel extension layers;
wherein each corresponding nanowire comprises silicon;
wherein outer edges of the second spacer layers are aligned with outer edges of the plurality of channel extension layers; and
wherein the outer edges of the plurality of channel extension layers are exposed edge surfaces of the plurality of channel extension layers.
2. The semiconductor device according to claim 1 , wherein the germanium concentration of each of the plurality of channel extension layers is at least 5% greater than the germanium concentration of its corresponding nanowire.
3. The semiconductor device according to claim 1 , wherein the second spacer layer comprises a dielectric.
4. The semiconductor device according to claim 3 , wherein the dielectric comprises at least one of silicon oxide, silicon nitride, silicon oxynitride, boron nitride, and silicon boron nitride.
5. The semiconductor device according to claim 1 , wherein the stacked configuration comprises a repeating arrangement of a plurality of semiconductor layers.
6. The semiconductor device according to claim 5 , wherein the plurality of semiconductor layers comprise silicon.
7. The semiconductor device according to claim 1 , wherein each of the plurality of channel extension layers is respectively positioned on a lateral side of its corresponding nanowire.
8. The semiconductor device according to claim 1 , wherein each second spacer layer respectively corresponds to and positioned adjacent at least one nanowire of the plurality of nanowires in the stacked configuration.
9. The semiconductor device according to claim 8 , wherein each second spacer layer is respectively positioned on lateral and upper or lower sides of the at least one nanowire.
10. A semiconductor device, comprising:
a stacked configuration comprising a repeating arrangement of a plurality of semiconductor layers in a channel region on a semiconductor substrate, wherein the channel region is defined by outer edges of a gate structure and outer edges of the plurality of semiconductor layers are aligned with the outer edges of the gate structure;
a plurality of channel extension layers extending from an outer edge of the channel region, each of the plurality of channel extension layers respectively corresponding to and positioned adjacent a semiconductor layer of the stacked configuration, wherein each of the plurality of channel extension layers has a higher germanium concentration than its corresponding semiconductor layer;
a first spacer layer formed adjacent the outer edge of the channel region on each of uppermost channel extension layers of the plurality of extension layers; and
a second spacer layer formed adjacent the outer edge of the channel region under each channel extension layer and under the first spacer layer;
wherein each of the plurality of channel extension layers comprises silicon germanium, wherein silicon comprises a first concentration and germanium comprises the remaining concentration of each of the plurality of channel extension layers;
wherein each corresponding semiconductor layer comprises silicon;
wherein outer edges of the second spacer layers are aligned with outer edges of the plurality of channel extension layers; and
wherein the outer edges of the plurality of channel extension layers are exposed edge surfaces of the plurality of channel extension layers.
11. The semiconductor device according to claim 10 , wherein the germanium concentration of each of the plurality of channel extension layers is at least 5% greater than the germanium concentration of its corresponding semiconductor layer.
12. The semiconductor device according to claim 10 , wherein the plurality of semiconductor layers comprise silicon.
13. The semiconductor device according to claim 10 , wherein each of the plurality of channel extension layers is respectively positioned on a lateral side of its corresponding semiconductor layer.
14. The semiconductor device according to claim 10 , wherein each second spacer layer respectively corresponds to and positioned adjacent at least one semiconductor layer of the stacked configuration.