IP Library › Granted Patent US 10,418,237
Granted Patent B2
US 10,418,237 · App. 15/820,803 · Granted Sep 17, 2019

Amorphous boron nitride dielectric

Inventors: Nicholas Glavin (Beavercreek, OH); Chris Muratore (Dayton, OH); Timothy Fisher (West Lafayette, IN); Andrey Voevodin (Denton, TX)
Assignee: United States of America as represented by the Secretary of the Air Force
H01L21/02172B82B1/002B82B1/008B82B3/0023B82B3/0038H01L21/02112H01L21/02266H01L29/2006H01L29/0665H01L29/1606
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Quick Facts
Patent No.
US 10,418,237
App. No.
15/820,803
Granted
Sep 17, 2019
Kind
B2
Abstract

A nanoelectronics structure is disclosed which includes a substrate layer which has least a first surface and also has a thickness of less than 100 nm. The nanoelectronics structure also includes a dielectric layer, which is deposited on the first surface of the substrate layer and has a thickness of less than 100 nm. This dielectric layer is made up of at least 90 mole percent amorphous boron nitride. Also disclosed is a method for forming a dielectric layer on a substrate using pulsed laser deposition.

Claims (17)

1. A nanoelectronics structure comprising:

a substrate layer having at least a first surface and having a thickness of less than 100 nm; and

a dielectric layer deposited on the first surface of the substrate layer and having a thickness of less than 100 nm,

wherein the dielectric layer comprises at least 90 mole percent amorphous boron nitride and exhibits a bandgap from about 4.0 eV to about 5.0 eV.

2. The nanoelectronics structure of claim 1 , wherein the dielectric layer comprises at least 95 mole percent amorphous boron nitride.

3. The nanoelectronics structure of claim 1 , wherein the substrate layer has a thickness of less than 20 nm.

4. The nanoelectronics structure of claim 1 , wherein the substrate layer comprises a material selected from the group consisting of silicon substrates, silicon oxide substrates, single-crystalline substrates, poly-crystalline substrates, polymer substrates, metal substrates, and two dimensional substrates.

5. The nanoelectronics structure of claim 1 , wherein the substrate layer comprises a material selected from the group consisting of tungsten, copper, silicon dioxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), molybdenum disulfide (MoS 2 ), graphene, polyethylene terephthalate (PET), and polydimethylsiloxane (PDMS).

6. The nanoelectronics structure of claim 1 , wherein the dielectric layer has a thickness of less than 20 nm.

7. The nanoelectronics structure of claim 1 , wherein the dielectric layer has a thickness of less than 10 nm.

8. The nanoelectronics structure of claim 1 , wherein the dielectric layer exhibits a dielectric constant from about 5.2 to about 6.6.

9. The nanoelectronics structure of claim 1 , wherein the dielectric layer exhibits a bandgap from about 4.3 eV to about 4.7 eV.

10. A nanoelectronics structure comprising:

a substrate layer having at least a first surface and having a thickness of less than 20 nm; and

a dielectric layer deposited on the first surface of the substrate layer and having a thickness of less than 20 nm,

wherein the substrate layer comprises a two-dimensional substrate material selected from the group consisting of molybdenum disulfide (MoS 2 ) and graphene, and

wherein the dielectric layer comprises at least 90 mole percent amorphous boron nitride.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 22, 2017
From: GLAVIN, NICHOLAS; MURATORE, CHRIS; VOEVODIN, ANDREY
To: GOVERNMENT OF THE UNITED STATES AS REPRESENTED BY THE SECRETARY OF THE AIR FORCE
Reel/Frame 044199/0242 →
Continuity (2)
Provisional Application 62425657 · Nov 23, 2016
Related Publication 20180144930A1 · May 24, 2018
Cited By (1)
US 12,654,197