IP Library Granted Patent US 10,418,459
Granted Patent B2
US 10,418,459 · App. 15/803,857 · Granted Sep 17, 2019

High electron mobility transistor including surface plasma treatment region

Inventors: Chih-Yen Chen (Tainan, TW); Hsien-Lung Yang (Taipei, TW)
Assignee: Wavetek Microelectronics Corporation
H01L29/66462H01L29/1045H01L29/1054H01L29/42376H01L29/7786H01L29/2003H01L29/207H01L29/4236H01L29/513
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Quick Facts
Patent No.
US 10,418,459
App. No.
15/803,857
Granted
Sep 17, 2019
Kind
B2
Abstract

A high electron mobility transistor includes a III-V compound layer, a nitride layer, a source electrode, a drain electrode, a gate electrode, a surface plasma treatment region, and at least one moat. The nitride layer is disposed on the III-V compound layer. The source and the drain electrodes are disposed above the III-V compound layer. The gate electrode is disposed above the nitride layer. The moat is at least partially disposed in the nitride layer and between the source and the drain electrodes. The surface plasma treatment region is at least partially disposed in the nitride layer. The surface plasma treatment region is at least partially disposed at a top surface of the nitride layer between the moat and the drain electrode, a top surface of the nitride layer between the moat and the source electrode, and/or a top surface of the nitride layer under the moat.

Claims (20)

1. A high electron mobility transistor (HEMT), comprising:

a III-V compound layer;

a nitride layer disposed on the III-V compound layer;

a source electrode and a drain electrode disposed above the III-V compound layer;

a gate electrode disposed over the nitride layer located between the source electrode and the drain electrode, wherein the nitride layer comprises a first region disposed under the gate electrode;

at least one moat at least partially disposed in the nitride layer and at least partially disposed between the source electrode and the drain electrode, wherein the at least one moat comprises a first moat and a second moat, the first moat is at least partially disposed between the first region and the source electrode, and the second moat is at least partially disposed between the first region and the drain electrode;

a fluorinated region disposed in the nitride layer, wherein at least a part of the fluorinated region is disposed in the first region of the nitride layer, and at least a part of the fluorinated region is disposed between the first moat and the second moat; and

a surface plasma treatment region at least partially disposed in the nitride layer, wherein the surface plasma treatment region is at least partially disposed at a top surface of the nitride layer disposed between the at least one moat and the drain electrode, at a top surface of the nitride layer disposed between the at least one moat and the source electrode, and/or at a top surface of the nitride layer under the at least one moat.

2. The HEMT of claim 1 , wherein the first moat and the second moat are separated from each other.

3. The HEMT of claim 1 , wherein the first moat and the second moat are connected with each other.

4. The HEMT of claim 3 , wherein a moat structure comprising the first moat and the second moat surrounds the first region of the nitride layer.

5. The HEMT of claim 1 , wherein at least a part of the surface plasma treatment region is disposed in the nitride layer located between the first moat and the source electrode.

6. The HEMT of claim 1 , wherein at least a part of the surface plasma treatment region is disposed in the nitride layer located between the second moat and the drain electrode.

7. The HEMT of claim 1 , wherein at least a part of the surface plasma treatment region is disposed in the nitride layer located between the first moat and the second moat.

8. The HEMT of claim 1 , wherein at least a part of the surface plasma treatment region is disposed in the nitride layer under the first moat.

9. The HEMT of claim 1 , wherein at least a part of the surface plasma treatment region is disposed in the nitride layer under the second moat.

10. The HEMT of claim 1 , wherein at least a part of the surface plasma treatment region is disposed at a sidewall of the first moat.

11. The HEMT of claim 1 , wherein at least a part of the surface plasma treatment region is disposed at a sidewall of the second moat.

12. The HEMT of claim 1 , wherein at least a part of the surface plasma treatment region is disposed above the fluorinated region in a thickness direction of the III-V compound layer.

13. The HEMT of claim 1 , wherein the surface plasma treatment region comprises a fluorine plasma region, and a fluorine concentration of the surface plasma treatment region is lower than a fluorine concentration of the fluorinated region.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 6, 2017
From: CHEN, CHIH-YEN; YANG, HSIEN-LUNG
To: WAVETEK MICROELECTRONICS CORPORATION
Reel/Frame 044035/0402 →
Priority Claims (1)
TW 106111881 · Apr 10, 2017 · national
Continuity (1)
Related Publication 20180294341A1 · Oct 11, 2018
Cited By (1)
US 12,426,296