Integrated circuit chip with strained NMOS and PMOS transistors

1. A method of simultaneously manufacturing N-channel and P-channel MOS transistors strained differently and respectively located in first and second side-by-side strips, the method comprising the steps of:

a) providing, on a substrate, a compressively strained layer that is located either under or over an assembly of a semiconductor layer arranged on an insulating layer;

b) etching through the compressively strained layer, the semiconductor layer and the insulating layer and into the substrate to form longitudinal trenches which extend between the first and second strips and on either side of the first and second strips;

c) etching through the compressively strained layer, the semiconductor layer and the insulating layer of the first strip and into the substrate to form transverse trenches which extend from one edge to another edge of the first strip;

wherein steps b) and c) form:

tensilely strained semiconductor slabs in the first strip between the transverse trenches, and

a semiconductor band in the second strip that is compressively strained in the direction of the longitudinal trenches and tensilely strained in the direction of the transverse trenches; and

d) forming transistors inside and on top of the semiconductor slabs and inside and on top of first portions of the semiconductor band located opposite the semiconductor slabs, while leaving in place second portions of the semiconductor band located opposite the transverse trenches.

2. The method of claim 1 , comprising, at step d), thermally oxidizing the second portions of the semiconductor band located opposite the transverse trenches all across a thickness of the semiconductor band.

3. The method of claim 1 , comprising:

at step d), forming insulated gates on the second portion of the semiconductor band located opposite the transverse trenches;

connecting the transistors to a source of high and low power supply potentials; and

connecting said insulated gates to a node of application of the high power supply potential.

4. The method of claim 1 , wherein the insulating layer is made of silicon oxide and the compressively strained layer is made of silicon nitride formed at step a) by plasma-enhanced chemical vapor deposition, the method comprising, after steps b) and c):

performing a thermal treatment of relaxation of the compressively strained layer capable of at least partly keeping the strain of the semiconductor band and of the semiconductor slabs; and

removing the compressively strained layer.

5. The method of claim 1 , wherein:

the substrate is made of silicon; and

the compressively strained layer is made of silicon-germanium and is grown by epitaxy at step a) on the substrate before forming the assembly of the insulating and semiconductor layers on the compressively strained layer.

6. The method of claim 1 , wherein said semiconductor layer is made of silicon in the two strips.

7. The method of claim 1 , comprising, at step a):

providing a silicon layer on the insulating layer;

epitaxially growing in the second strip a silicon-germanium layer on the silicon layer; and

thermally oxidizing the structure in the second strip,

whereby said semiconductor layer is made of silicon in the first strip and of silicon-germanium in the second strip.

8. The method of claim 1 , wherein steps b) and c) are formed simultaneously and the transverse and longitudinal trenches have a same depth.

9. The method of claim 1 , comprising a step of forming a doped semiconductor well under the insulating layer in the first strip, the longitudinal trenches extending deeper than the doped semiconductor well, and the transverse trenches extending all the way to a level located in the doped semiconductor well.

10. A method, comprising the steps of:

a) providing a compressively strained nitride layer over a semiconductor layer arranged on an insulating layer supported by a substrate;

b) etching longitudinal trenches through the compressively strained nitride layer, the semiconductor layer, the insulating layer and partially into the substrate to form first and second semiconductor strips;

c) etching transverse trenches through the compressively strained nitride layer, the semiconductor layer, the insulating layer and partially into the substrate to form a plurality of semiconductor slabs from the first semiconductor strip;

wherein steps b) and c) produce:

tensile strain both longitudinally and transversely in each semiconductor slab of said plurality of semiconductor slabs; and

tensile strain transversely in the second semiconductor strip while maintaining compressive strain longitudinally in the second semiconductor strip;

d) forming transistors of a first conductivity type inside and on top of the semiconductor slabs;

e) forming transistors of a second conductivity type inside and on top of the second semiconductor strip.

11. The method of claim 10 , further comprising locating the transistors of the second conductivity type in first portions of the second semiconductor strip located transversally opposite the semiconductor slabs.

12. The method of claim 11 , further comprising leaving second portions of the second semiconductor strip in place transversely opposite the transverse trenches.

13. The method of claim 12 , comprising, thermally oxidizing the second portions of the second semiconductor strip to form oxide bars transversely extending across the second semiconductor strip to delimit further semiconductor slabs.

14. The method of claim 13 , further comprising locating the transistors of the second conductivity type in the further semiconductor slabs which are located transversally opposite the semiconductor slabs.

15. The method of claim 13 , wherein thermally oxidizing comprises thermally oxidizing across an entire thickness of the second semiconductor strip.

16. The method of claim 12 , further comprising forming insulated gates for the transistors of the first and second conductivity type which extend over the location of the second portions of the second semiconductor strip.

17. The method of claim 10 , further comprising, prior to step a):

providing a silicon layer on the insulating layer;

epitaxially growing a silicon-germanium layer on a portion of the silicon layer corresponding to a location of the second semiconductor strip; and

thermally oxidizing to convert the portion of the silicon layer to a compressively strained semiconductor portion from which the second semiconductor strip is formed.

18. The method of claim 10 , wherein the transverse and longitudinal trenches have a same depth.

19. A method, comprising the steps of:

a) providing a compressively strained nitride layer over a semiconductor layer arranged on an insulating layer supported by a substrate, wherein said semiconductor layer includes a first portion which is not strained and a second portion which is compressively strained;

b) etching longitudinal trenches through the compressively strained nitride layer, the semiconductor layer, the insulating layer and partially into the substrate to form a first semiconductor strip from the first portion and a second semiconductor strip from the second portion;

c) etching transverse trenches through the compressively strained nitride layer, the semiconductor layer, the insulating layer and partially into the substrate to form a plurality of semiconductor slabs from the first semiconductor strip;

wherein steps b) and c) produce:

tensile strain both longitudinally and transversely in each semiconductor slab of said plurality of semiconductor slabs; and

tensile strain transversely in the second semiconductor strip while maintaining compressive strain longitudinally in the second semiconductor strip;

d) forming transistors of a first conductivity type inside and on top of the semiconductor slabs;

e) forming transistors of a second conductivity type inside and on top of the second semiconductor strip.

20. The method of claim 19 , further comprising locating the transistors of the second conductivity type in first portions of the second semiconductor strip located transversally opposite the semiconductor slabs.

21. The method of claim 11 , further comprising:

leaving second portions of the second semiconductor strip in place transversely opposite the transverse trenches; and

thermally oxidizing the second portions of the second semiconductor strip to form oxide bars transversely extending across the second semiconductor strip to delimit further semiconductor slabs.

22. The method of claim 21 , further comprising locating the transistors of the second conductivity type in the further semiconductor slabs which are located transversally opposite the semiconductor slabs.

23. The method of claim 21 , further comprising forming insulated gates for the transistors of the first and second conductivity type which extend over the location of the second portions of the second semiconductor strip.

24. The method of claim 19 , wherein the transverse and longitudinal trenches have a same depth.