Ultra-short RFFE datagrams for latency sensitive radio frequency front-end

1. A method performed at a device operating as a bus master, comprising:

configuring a slave device coupled to a multi-wire serial bus for entry to a low-latency mode of communication using signaling transmitted on the multi-wire serial bus, wherein the signaling includes a first pulse transmitted on a first wire of the multi-wire serial bus and a second pulse transmitted on a second wire of the multi-wire serial bus while the first pulse is present on the first wire of the multi-wire serial bus, wherein the second pulse is shorter in duration than the first pulse;

initiating the low-latency mode of communication immediately after termination of the first pulse; and

transmitting information to the slave device in a datagram, wherein the datagram is configured for the low-latency mode of communication.

2. The method of claim 1 , further comprising:

configuring a register that defines structure of the datagram; and

transmitting the datagram during the low-latency mode of communication.

3. The method of claim 2 , wherein configuring the register that defines the structure of the datagram includes:

configuring a number of bits to represent a slave device address transmitted in the datagram.

4. The method of claim 3 , wherein the slave device address is represented by between 2 and 4 bits.

5. The method of claim 2 , wherein configuring the register that defines the structure of the datagram includes:

configuring a number of bits to represent a register address transmitted in the datagram.

6. The method of claim 5 , wherein the register address is represented by between 2 and 8 bits.

7. The method of claim 5 , further comprising:

configuring a destination register that identifies a base register in a block of registers to be addressed using the register address in the datagram.

8. The method of claim 2 , wherein configuring the register that defines the structure of the datagram includes:

configuring a number of bits to carry a payload in the datagram.

9. The method of claim 8 , wherein the payload is carried in between 2 and 8 bits.

10. The method of claim 2 , further comprising:

writing the register that defines the structure of the datagram to at least one slave device.

11. The method of claim 2 , further comprising:

transmitting the datagram using double-data rate encoding.

12. The method of claim 2 , further comprising:

selecting a configuration for the datagram to be transmitted during the low-latency mode of communication,

wherein a difference in durations of the first pulse and the second pulse indicates the selected configuration of the datagram.

13. An apparatus, comprising:

a bus interface configured to couple the apparatus to a slave device through a serial bus; and

a processing circuit configured to:

configure the slave device coupled to the serial bus for entry to a low-latency mode of communication using signaling transmitted on the serial bus, wherein the signaling includes a first pulse transmitted on a first wire of the serial bus and a second pulse transmitted on a second wire of the serial bus while the first pulse is present on the first wire of the serial bus, wherein the second pulse is shorter in duration than the first pulse;

initiate the low-latency mode of communication immediately after termination of the first pulse; and

transmit information to the slave device in a datagram, wherein the datagram is configured for the low-latency mode of communication.

14. The apparatus of claim 13 , wherein the processing circuit is further configured to:

configure a register that defines structure of the datagram; and

transmit the datagram during the low-latency mode of communication.

15. The apparatus of claim 14 , wherein the processing circuit configures the register that defines the structure of the datagram by:

configuring a number of bits to represent a slave device address or a register address transmitted in the datagram.

16. The apparatus of claim 14 , wherein the processing circuit configures the register that defines the structure of the datagram by:

configuring a number of bits to carry a payload in the datagram.

17. A method performed at a slave device coupled to a multi-wire serial bus, comprising:

detecting a first pulse in signaling state of a first wire of the multi-wire serial bus;

detecting a second pulse in signaling state of a second wire of the multi-wire serial bus while the first pulse is present in the signaling state of the first wire of the multi-wire serial bus, wherein the second pulse is shorter in duration than the first pulse;

entering a low-latency mode of communication immediately after termination of the first pulse; and

transmitting information to another device in a datagram configured for the low-latency mode of communication.

18. The method of claim 17 , further comprising:

determining a structure of the datagram from bit settings of a first configuration register,

wherein the first configuration register defines a number of bits used to represent an address transmitted in the datagram.

19. The method of claim 18 , wherein the first configuration register defines a number of bits used to represent a slave address transmitted in the datagram, and wherein the slave address is represented in a field that has a length of between 2 and 4 bits.

20. The method of claim 18 , wherein the first configuration register defines a number of bits used to represent a register address in the datagram, and wherein the register address is represented in a field that has a length of between 2 and 8 bits.

21. The method of claim 20 , further comprising:

using the register address in the datagram to identify a target register in a block of registers, the block of registers commencing at an address identified by a second configuration register; and

writing payload data transmitted in the datagram to the target register.

22. The method of claim 20 , further comprising:

using the register address in the datagram to identify a target register in a block of registers, the block of registers commencing at an address identified by a second configuration register; and

transmitting data read from the target register as payload data in the datagram.

23. The method of claim 18 , wherein the first configuration register defines a number of bits used to carry a payload in the datagram.

24. The method of claim 23 , wherein the payload is carried in between 2 and 8 bits of the datagram.

25. The method of claim 18 , further comprising:

transmitting the datagram on the multi-wire serial bus using double-data rate encoding.

26. An apparatus, comprising:

a bus interface configured to couple the apparatus to a multi-wire serial bus;

a plurality of configuration registers; and

a processing circuit configured to:

detect a first pulse in signaling state of a first wire of the multi-wire serial bus;

detect a second pulse in signaling state of a second wire of the multi-wire serial bus while the first pulse is present in the signaling state of the first wire of the multi-wire serial bus, wherein the second pulse is shorter in duration than the first pulse;

cause the bus interface to enter a low-latency mode of communication immediately after termination of the first pulse; and

cause the bus interface to transmit information to another device in a datagram configured for the low-latency mode of communication.

27. The apparatus of claim 26 , wherein the processing circuit is adapted further configured to:

determine a structure of the datagram from bit settings of a first configuration register,

wherein the first configuration register defines a number of bits used to represent an address transmitted in the datagram.

28. The apparatus of claim 27 , wherein the first configuration register defines a number of bits used to represent a slave address or a register address transmitted in the datagram, and wherein the number of bits lies between 2 and 8 bits.

29. The apparatus of claim 28 , further comprising:

a block of bus-accessible registers, wherein the register address in the datagram is used to identify a target register in the block of bus-accessible registers, the block of bus-accessible registers commencing at an address identified by a second configuration register, and

wherein the processing circuit is further configured to write payload data transmitted in the datagram to the target register.

30. The apparatus of claim 28 , further comprising:

a block of bus-accessible registers, wherein the register address in the datagram is used to identify a target register in the block of bus-accessible registers, the block of bus-accessible registers commencing at an address identified by a second configuration register, and

wherein the processing circuit is further configured to transmit data read from the target register as payload data in the datagram.