Display flicker reduction systems and methods
Aspects of the subject technology relate to electronic devices with displays. A display may include an array of display pixels each having a drive transistor and an organic light-emitting diode. A pulse-width-modulated current may be provided to the organic light-emitting diode during each display frame to compensate for an on-bias compensation applied to the drive transistor between display frames. The pulse-width-modulated current may be provided with a pulse-width-modulation ratio that decreases over the course of each display frame. The decrease of the pulse-width-modulation ratio for each display frame may be determined based on a peak luminance for that display frame. The reduction in flicker provided by the pulse-width-modulated current may facilitate operation of the display with a reduced refresh rate, thereby reducing power consumption by the display.
1. A method, comprising:
operating, during a first display frame, a drive transistor of a pixel circuit of an electronic device display to provide a first current to a light-emitting element of the pixel circuit;
providing, after the first display frame, a bias stress compensation to the drive transistor; and
providing, after providing the bias stress compensation and during a second display frame, a pulse-width-modulated current to the light-emitting element of the pixel circuit by compensating for an overshoot and decay of a threshold voltage of the drive transistor caused by provided on-bias stress.
2. The method of claim 1 , wherein providing the bias stress compensation comprises providing an on-bias stress compensation to the drive transistor that resets a threshold voltage of the drive transistor to compensate for a bias stress effect in the drive transistor, the bias stress effect associated with at least the first display frame.
3. The method of claim 1 , wherein providing the pulse-width-modulated current to the light-emitting element of the pixel circuit reduces display flicker for the electronic device display.
4. The method of claim 1 , wherein providing the pulse-width-modulated current comprises modulating a second current to the light-emitting element with a pulse-width-modulation ratio that decays during the second display frame.
5. The method of claim 4 , wherein the pulse-width-modulation ratio decays at a decay rate that corresponds to a rate of the decay of the threshold voltage.
6. The method of claim 5 , further comprising, determining the decay rate based on a peak luminance across a plurality of display pixels of the electronic device display for the second display frame.
7. The method of claim 6 , further comprising determining a minimum available refresh rate for the second display frame based on the peak luminance.
8. The method of claim 6 , wherein the light-emitting element comprises an organic light-emitting diode, wherein the electronic device display is an organic light-emitting diode display that comprises an array of active organic light-emitting diode display pixels, and wherein the plurality of display pixels comprises all of the active organic light-emitting diode display pixels.
9. The method of claim 6 , wherein the light-emitting element comprises an organic light-emitting diode, wherein the electronic device display is an organic light-emitting diode display that comprises an array of active organic light-emitting diode display pixels, and wherein the plurality of display pixels comprises a subset of the active organic light-emitting diode display pixels.
10. The method of claim 6 , wherein the light-emitting element comprises an organic light-emitting diode, wherein the electronic device display is an organic light-emitting diode display that comprises an array of active organic light-emitting diode display pixels, and wherein the method further comprises:
providing, to each of the active organic light-emitting diode display pixels, a pulse-width-modulated input voltage with the decay rate based on the peak luminance.
11. An electronic device having a display with an array of display pixels each having a drive transistor and a light-emitting diode coupled to the drive transistor, the electronic device comprising:
display control circuitry configured to:
operate, during a first display frame, the drive transistors of the array of display pixels to provide display currents to the light-emitting diodes of the array of display pixels;
provide, after the first display frame, bias stress compensation voltages to the drive transistors of the array of display pixels; and
provide, after providing the bias stress compensation voltages and during a second display frame, pulse-width-modulated currents to the light-emitting diodes of the array of display pixels by compensating for an overshoot and decay of a threshold voltage of the drive transistor caused by provided on-bias stress.
12. The electronic device of claim 11 , wherein the light-emitting diodes comprise organic light-emitting diodes, and wherein the display control circuitry is further configured to adjust a length of the second display frame based, at least in part, on a reduced flicker provided by the pulse-width-modulated currents.
13. The electronic device of claim 12 , wherein the display control circuitry is configured to adjust the length of the second display frame based on a peak luminance across the array of display pixels for the second display frame.
14. The electronic device of claim 11 , wherein the display control circuitry is configured to provide the pulse-width-modulated currents to the light-emitting diodes of the array of display pixels based on a peak luminance, over the array of display pixels, for the second display frame.
15. The electronic device of claim 11 , wherein the display control circuitry is configured to provide the pulse-width-modulated currents to the light-emitting diodes of the array of display pixels by modulating a pixel-specific display current for each display pixel with a global pulse-width modulation.
16. The electronic device of claim 11 , wherein the display control circuitry is configured to provide the pulse-width-modulated currents to the light-emitting diodes of the array of display pixels by modulating a pixel-specific display current for each display pixel with a regional pulse-width modulation that is specific to a region of the array of display pixels.
17. The electronic device of claim 11 , wherein the display control circuitry is configured to provide the pulse-width-modulated currents to the light-emitting diodes of the array of display pixels by modulating a pixel-specific display current for each display pixel with a pixel-specific pulse-width modulation.
18. An electronic device having a display with an array of display pixels, the electronic device comprising:
display control circuitry configured to:
provide, following a first display frame, a bias stress compensation to the array of display pixels to compensate for a bias stress effect associated with at least the first display frame; and
operate, during a second display frame that follows the bias stress compensation, the array of display pixels to provide pulse-width-modulated input signals to reduce a flicker generated by the bias stress compensation by compensating for an overshoot and decay of a threshold voltage of a drive transistor caused by provided on-bias stress.
19. The electronic device of claim 18 , wherein the array of display pixels comprises an array of organic light-emitting diode display pixels, wherein the pulse-width-modulated input signals have a common pulse-width ratio, and wherein the display control circuitry is configured to reduce the pulse-width ratio during progression of the second display frame.
20. The electronic device of claim 19 , wherein the display control circuitry is configured to reduce the pulse-width ratio based on a peak luminance, across the array of display pixels, for the second display frame.
21. The electronic device of claim 19 , wherein the bias stress compensation is an on-bias stress compensation.
22. The electronic device of claim 18 , wherein the bias stress compensation is an off-bias stress compensation, wherein the pulse-width-modulated input signals have a common pulse-width ratio, and wherein the display control circuitry is configured to increase to the pulse-width ratio during progression of the second display frame.
23. The electronic device of claim 18 , wherein the display control circuitry is further configured to determine a decay rate for the pulse-width-modulated input signals based on a peak luminance over the array of display pixels for the second display frame.
24. An electronic device having a display with an array of display pixels, the electronic device comprising:
display control circuitry configured to:
provide, following a first display frame, a bias stress compensation to the array of display pixels to compensate for a bias stress effect associated with at least the first display frame, wherein the bias stress compensation is based on a luminance associated with a second display frame that follows the bias stress compensation; and
operate, during the second display frame that follows the bias stress compensation, the array of display pixels to provide pulse-width-modulated input signals to reduce a flicker generated by the bias stress compensation by compensating for an overshoot and decay of a threshold voltage of a drive transistor caused by provided on-bias stress.
25. The electronic device of claim 24 , wherein the pulse-width-modulated input signals are independent of the luminance associated with the second display frame.
26. The electronic device of claim 24 , wherein the luminance associated with the second display frame is a peak luminance of the second display frame.
27. The electronic device of claim 24 , wherein the luminance associated with the second display frame is an average luminance of the second display frame.
28. The electronic device of claim 24 , wherein the bias stress compensation comprises an application of a bias voltage to a drive transistor of each display pixel of the array of display pixels, and wherein the bias voltage comprises a voltage shift relative to a display voltage corresponding to the luminance associated with the second display frame.