Nanosheet transistor with high-mobility channel
A method of fabricating a semiconductor device includes forming a gate on a nanosheet stack including a first nanosheet and a second nanosheet. The first nanosheet and the second nanosheet each include a dielectric material. The method includes removing a portion of the nanosheet stack in a source/drain region adjacent to the gate to form a trench and depositing a first semiconductor material in the trench. The method further includes removing the second nanosheet from the nanosheet stack to form a channel region gap in the nanosheet stack and depositing a second semiconductor material in the channel region gap to form a channel.
1. A method of fabricating a semiconductor device, the method comprising:
forming a gate on a nanosheet stack consisting essentially of alternating single layers of a first nanosheet and a second nanosheet, the first nanosheet and the second nanosheet each comprising a dielectric material;
removing a portion of the nanosheet stack in a source/drain region adjacent to the gate to form a trench;
depositing a first semiconductor material in the trench;
removing the second nanosheet from the nanosheet stack to form a channel region gap in the nanosheet stack; and
depositing a second semiconductor material in the channel region gap to form a channel.
2. The method of claim 1 , wherein depositing the first semiconductor material in the trench comprises an aspect ratio trapping process.
3. The method of claim 2 , wherein the first semiconductor material comprises silicon germanium, germanium or a III-V material.
4. The method of claim 1 further comprising, subsequent to depositing the first semiconductor material in the trench, removing a portion of the nanosheet stack in another source/drain region adjacent to the gate to form a second trench, and then depositing the second semiconductor material in the second trench.
5. The method of claim 1 , wherein depositing the second semiconductor material in the channel region gap comprises an epitaxial growth process.
6. The method of claim 5 , wherein the second semiconductor material comprises silicon germanium, germanium or a III-V material.
7. The method of claim 1 further comprising removing the first and second semiconductor materials from the trench and depositing a third semiconductor material to form a source/drain, and the third semiconductor material comprises a semiconductor material that is different than the channel.
8. A method of fabricating a semiconductor device, the method comprising:
forming a gate on a nanosheet stack consisting essentially of alternating single layers of a first nanosheet and a second nanosheet, the first nanosheet and the second nanosheet each comprising a dielectric material, and the nanosheet stack arranged on a nitride layer;
removing a portion of the nanosheet stack in a source/drain region adjacent to the gate to form a trench;
depositing a first semiconductor material in the trench;
removing the second nanosheet from the nanosheet stack to form a channel region gap in the nanosheet stack; and
depositing a second semiconductor material in the channel region gap to form a channel, the second semiconductor material comprising silicon germanium, germanium or a III-V material.
9. The method of claim 8 , wherein depositing the first semiconductor material in the trench comprises an aspect ratio trapping process.
10. The method of claim 9 , wherein the first semiconductor material comprises silicon germanium, germanium or a III-V material.
11. The method of claim 8 further comprising, after depositing the first semiconductor material in the trench, removing a portion of the nanosheet stack in another source/drain region adjacent to the gate to form a second trench, and then depositing the second semiconductor material in the second trench.
12. The method of claim 8 , wherein depositing the second semiconductor material in the channel region gap comprises an epitaxial growth process.
13. The method of claim 12 , wherein the second semiconductor material comprises silicon germanium, germanium or a III-V material.
14. The method of claim 8 further comprising removing the first and second semiconductor materials from the trench and depositing a third semiconductor material to form a source/drain, and the third semiconductor material comprises a semiconductor material that is different than the channel.
15. A semiconductor device comprising:
a nanosheet channel comprising silicon germanium, germanium or a III-V material arranged on a substrate;
a nitride layer is arranged in the substrate, the nanosheet channel arranged on the nitride layer;
a gate arranged on the nanosheet channel; and
a source/drain adjacent to the channel.
16. The semiconductor device of claim 15 , wherein the substrate comprises silicon.
17. The semiconductor device of claim 15 , wherein the source/drain comprises silicon germanium, germanium or a III-V material.
18. The semiconductor device of claim 15 , wherein the source/drain comprises a material that is different than the nanosheet channel.
19. The semiconductor device of claim 15 , wherein the nanosheet channel comprises and epitaxial growth.
20. The method of claim 8 , wherein the nitride layer comprises silicon nitride.