Granted Patent B2

US 12,191,352 · App. 17/483,870 · Granted Jan 7, 2025

Inventors: Takashi Ando (Eastchester, NY); Ruilong Xie (Niskayuna, NY); Pouya Hashemi (Purchase, NY); Alexander Reznicek (Troy, NY)

Assignee: International Business Machines Corporation

H01L29/0673H01L27/0886H01L29/0653H01L29/41791H01L29/42364H01L29/785

Abstract

Claims (98)

1. An integrated circuit (IC) having transistor devices comprising a first transistor type, the first transistor type comprising:

a channel stack comprising first stacked, spaced-apart, channel layers;

wherein a first one of the first stacked, spaced-apart channel layers comprises a first trimmed channel region and first non-trimmed channel regions;

a first source or drain (S/D) region communicatively coupled to the channel stack;

a tunnel extending through the channel stack;

wherein a first portion of a boundary of the tunnel is defined by the first trimmed channel region;

wherein the tunnel comprises a central region and a first set of end regions;

wherein the first set of end regions is closer to the first S/D region than the central region is to the first S/D region;

a first type of work-function metal (WFM) formed in the first set of end regions, the first WFM having a first work-function (WF); and

a second type of WFM formed in the central region, the second type of WFM having a second WF;

wherein the first WF is different than the second WF.

2. The IC of claim 1 further comprising a second S/D region communicatively coupled to the channel stack.

3. The IC of claim 2 , wherein the tunnel further comprises a second set of end regions.

4. The IC of claim 3 , wherein the second set of end regions is closer to the second S/D region than the central region is to the second S/D region.

5. The IC of claim 4 , wherein the first type of WFM is formed in the second set of end regions.

6. The IC of claim 1 further comprising inner spacers.

7. The IC of claim 6 , wherein a second portion of the boundary of the tunnel comprises a set of the inner spacers.

8. The IC of claim 7 , wherein:

the boundary of the tunnel further comprises a second one of the stacked, spaced-apart channel layers;

the second one of the stacked, spaced-apart channel layers comprises a second trimmed channel region and second non-trimmed channel regions; and

a third portion of the boundary of the tunnel is defined by the second trimmed channel region.

9. The IC of claim 1 further comprising:

a gate dielectric within the tunnel;

wherein the first type of WFM comprises:

a first layer of metal having a first thickness;

a layer of an aluminum alloy; and

a second layer of metal;

wherein the second type of WFM comprises:

a third layer of metal having a second thickness;

a layer of an aluminum alloy; and

a fourth layer of metal; and

wherein the first thickness is less than the second thickness.

10. The IC of claim 9 , wherein the transistor devices comprise a second transistor type, the second transistor type comprising:

a second-transistor-type channel stack comprising second stacked, spaced-apart, channel layers;

wherein a first one of the second stacked, spaced-apart channel layers comprises a second trimmed channel region and second non-trimmed channel regions;

a second-transistor-type S/D region communicatively coupled to the second-transistor-type channel stack;

a second-transistor-type tunnel extending through the second-transistor-type channel stack;

wherein a first portion of a boundary of the second-transistor-type tunnel is defined by the second trimmed channel region;

a second-transistor-type gate dielectric within the second-transistor-type tunnel;

wherein the second-transistor-type tunnel comprises a second-transistor-type central region and a second-transistor-type set of end regions;

wherein the second-transistor-type set of end regions is closer to the second-transistor-type S/D region than the second-transistor-type central region is to the second-transistor-type S/D region;

a first type of second-transistor-type work-function metal (WFM) formed in the second-transistor-type set of end regions, the first WFM having a first work-function (WF); and

a second type of second-transistor-type WFM formed in the central region, the second type of WFM having a second WF;

wherein the first type of second-transistor-type WFM comprises a first layer of metal; and

wherein the second type of second-transistor-type WFM comprises:

a second layer of metal having a predetermined thickness;

a layer of an aluminum alloy; and

a third layer of metal;

wherein the predetermined thickness is greater than the second thickness.

11. A method of forming an integrated circuit (IC) having transistor devices comprising a first transistor type, the method comprising forming the first transistor type by performing fabrication operations comprising:

forming a channel stack comprising first stacked, spaced-apart, channel layers;

wherein a first one of the first stacked, spaced-apart channel layers comprises a first trimmed channel region and first non-trimmed channel regions;

forming a first source or drain (S/D) region communicatively coupled to the channel stack;

forming a tunnel extending through the channel stack;

wherein a first portion of a boundary of the tunnel is defined by the first trimmed channel region;

wherein the tunnel comprises a central region and a first set of end regions;

wherein the first set of end regions is closer to the first S/D region than the central region is to the first S/D region;

forming a first type of work-function metal (WFM) in the first set of end regions, the first WFM having a first work-function (WF); and

forming a second type of WFM in the central region, the second type of WFM having a second WF;

wherein the first WF is different than the second WF.

12. The method of claim 11 further comprising forming a second S/D region communicatively coupled to the channel stack.

13. The method of claim 12 , wherein the tunnel further comprises a second set of end regions.

14. The method of claim 13 , wherein the second set of end regions is closer to the second S/D region than the central region is to the second S/D region.

15. The method of claim 14 , wherein the first type of WFM is formed in the second set of end regions.

16. The method of claim 11 , wherein forming the tunnel comprises:

forming a set of inner spacers that extend under a gate structure of the transistor device; and

forming the first trimmed channel region.

17. The method of claim 16 , wherein the boundary of the tunnel comprises the set of the inner spacers.

18. The method of claim 17 , wherein:

the method further comprises forming a second one of the first stacked, spaced-apart channel layers;

wherein the second one of the first stacked, spaced-apart channel layers comprises a second trimmed channel region and second non-trimmed channel regions; and

the boundary of the tunnel further comprises the second trimmed channel region.

19. The method of claim 11 further comprising:

forming a gate dielectric within the tunnel;

wherein the first type of WFM comprises:

a first layer of metal having a first thickness;

a layer of an aluminum alloy; and

a second layer of metal; and

wherein the second type of WFM comprises:

a third layer of metal having a second thickness;

a layer of an aluminum alloy; and

a fourth layer of metal;

wherein the first thickness is less than the second thickness.

20. The method of claim 19 , wherein the transistor devices comprise a second transistor type and the fabrication operations further comprise:

forming a second-transistor-type channel stack comprising stacked, spaced-apart, channel layers;

forming a second-transistor-type S/D region communicatively coupled to the second-transistor-type channel stack;

forming a second-transistor-type tunnel extending through the second-transistor-type channel stack;

forming a second-transistor-type gate dielectric within the second-transistor-type tunnel;

wherein the second-transistor-type tunnel comprises a second-transistor-type central region and a second-transistor-type set of end regions;

wherein the second-transistor-type set of end regions is closer to the second-transistor-type S/D region than the second-transistor-type central region is to the second-transistor-type S/D region;

forming a first type of second-transistor-type WFM formed in the second-transistor-type set of end regions, the first WFM having a first work-function (WF); and

forming a second type of second-transistor-type WFM formed in the central region, the second type of WFM having a second WF;

wherein the first type of second-transistor-type WFM comprises a first layer of metal; and

wherein the second type of second-transistor-type WFM comprises:

a second layer of metal having a predetermined thickness;

a layer of an aluminum alloy; and

a third layer of metal;

wherein the predetermined thickness is greater than the second thickness.

Assignments (1)

Continuity (1)

References Cited (18)

Cited By (1)

US 12,564,032