IP Library Granted Patent US 10,424,663
Granted Patent B2
US 10,424,663 · App. 15/813,523 · Granted Sep 24, 2019

Super long channel device within VFET architecture

Inventors: Marc A. Bergendahl (Troy, NY); Kangguo Cheng (Schenectady, NY); Gauri Karve (Cohoes, NY); Fee Li Lie (Albany, NY); Eric R. Miller (Schenectady, NY); John R. Sporre (Albany, NY); Sean Teehan (Rensselaer, NY)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
H01L29/7827H01L29/0847H01L29/1037H01L29/6656H01L29/66666H01L29/78642H03K17/687H01L29/0653H01L29/4958H01L29/4966H01L29/517H01L29/518
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Quick Facts
Patent No.
US 10,424,663
App. No.
15/813,523
Granted
Sep 24, 2019
Kind
B2
Abstract

Embodiments are directed to methods and resulting structures for a vertical field effect transistor (VFET) having a super long channel. A pair of semiconductor fins is formed on a substrate. A semiconductor pillar is formed between the semiconductor fins on the substrate. A region that extends under all of the semiconductor fins and under part of the semiconductor pillar is doped. A conductive gate is formed over a channel region of the semiconductor fins and the semiconductor pillar. A surface of the semiconductor pillar serves as an extended channel region when the gate is active.

Claims (14)

1. A method for forming a semiconductor device, the method comprising:

forming a pair of semiconductor fins on a substrate;

forming a semiconductor pillar between the semiconductor fins on the substrate;

forming a bottom doped region that extends under all of the semiconductor fins and under part of the semiconductor pillar;

recessing the semiconductor pillar below a surface of the semiconductor fins; and

forming a conductive gate over a channel region of the semiconductor fins and the semiconductor pillar.

2. The method of claim 1 further comprising doping the semiconductor pillar.

3. The method of claim 1 further comprising forming a thick oxide layer between the conductive gate and the semiconductor fins and the semiconductor pillar.

4. The method of claim 1 further comprising forming a bottom spacer between the conductive gate and the bottom doped region.

5. The method of claim 1 further comprising forming a top spacer on the conductive gate.

6. The method of claim 1 further comprising forming top doped regions on exposed surfaces of the semiconductor fins.

7. The method of claim 6 further comprising forming a conductive contact on the top doped regions.

8. The method of claim 7 further comprising forming a gate contact on the conductive gate and over the semiconductor pillar.

9. The method of claim 1 , wherein a thickness of the semiconductor pillar is larger than a thickness of the semiconductor fins.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 15, 2017
From: BERGENDAHL, MARC A.; CHENG, KANGGUO; KARVE, GAURI; LIE, FEE LI; MILLER, ERIC R.; SPORRE, JOHN R.; TEEHAN, SEAN
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 044137/0421 →
Continuity (2)
Continuation 15602884 · May 23, 2017
Related Publication 20180342615A1 · Nov 29, 2018
Cited By (1)
US 12,356,685