Chip and application thereof
Disclosed is a chip. The chip comprises a substrate ( 1 ) and a base layer ( 2 ) in pressing arrangement with the substrate; the substrate comprises a first surface ( 1 a ) and a second surface ( 1 b ) in opposite arrangement, reaction tank arrays formed by a plurality of flowing channels ( 11 ) are arranged on the first surface of the substrate at intervals, two oppositely arranged side walls ( 111, 112 ) of each flowing channel ( 11 ) stretch along the length direction of the flowing channel ( 11 ) and intersect at two ends of the flowing channel to form two tapered tail ends ( 113 ) with included angles, and a fluid inlet hole ( 12 ) and a fluid outlet hole ( 13 ) which are communicated with the second surface of the substrate are respectively provided on the surfaces of the two tapered tail ends ( 113 ); and the base layer ( 2 ) comprises a transparent base ( 21 ) and a spacing layer ( 22 ) arranged on the surface of the transparent base, the spacing layer ( 22 ) is in contact with the firs surface ( 1 a ) of the substrate, and a corrosion groove is provided on the spacing layer ( 22 ) corresponding to a position where the flowing channel ( 11 ) is located. The flow field distribution of the chip is good, the deformation rate of a base in the chip is low, and the fluid in the chip can be fully flushed or replaced. Also disclosed is an application of the chip.
1. A chip for single molecule sequencing, comprising a substrate and a base layer in contact with the substrate, wherein
the substrate comprises a first surface and a second surface which are arranged oppositely,
an array including multiple channels arranged on the first surface of the substrate at intervals,
two oppositely arranged side walls of each of the channels stretching along a longitudinal direction of a respective channel and intersecting at two ends of the respective channel to form two tapered tail ends with included angles, a distance between the two oppositely arranged side walls of each of the channels is a width of each of the channels, and the width of each of the channels is 1 to 2 mm, the distance between intersections of the two oppositely arranged side walls of each of the channels is a length of each of the channels, and the length of each of the channels is 50 to 75 mm; and
an inlet hole and an outlet hole connected with the second surface being respectively provided on the two tapered tail ends; and
the base layer comprises a transparent layer and a spacing layer arranged on a portion of a surface of the transparent layer between each of the channels, the spacing layer being a portion of the side walls of each of the channels,
the spacing layer is a polymethylglutarimide layer,
the spacing layer being in contact with the first surface of the substrate, and
grooves being provided on the spacing layer corresponding to positions where the channels are located.
2. A chip according to claim 1 , wherein the array includes 15 to 25 channels.
3. A chip according to claim 1 , wherein the width of the spacing layer along a direction perpendicular to the longitudinal direction of the respective channel is 1 to 1.5 mm.
4. A chip according to claim 1 , wherein a depth of each channel is 0.6 to 1 mm.
5. A chip according to claim 1 , wherein a diameter of the inlet hole is 300 to 500 μm, and a diameter of the outlet hole is 300 to 500 μm.
6. A chip according to claim 1 , wherein the included angles at the tapered tail ends are 30° to 60°.
7. A chip according to claim 1 , wherein a material of the substrate is selected from one or more of polydimethylsiloxane, polymethylmethacrylate, ethylene-vinyl acetate and polyurethane.
8. A chip according to claim 1 , wherein a depth of each groove is 1 to 5 μm.
9. A chip according to claim 1 , wherein the chip further includes a probe immobilized on the surface of the transparent layer of the chip, and the surface of the transparent layer is modified to have one or more of epoxy group, amino group, carboxyl, sulfydryl and aldehyde group.