Speeding up transactions in non-volatile memory using hardware transactional memory
The disclosure provides an approach for atomically executing computer instructions by a CPU of a computing device comprising non-volatile memory, the CPU configured to implement hardware transactional memory (HTM). The approach generally includes reading an instruction within a section of code designated as an HTM transaction, determining whether the instruction causes a data conflict with another thread, and copying cache lines from memory into a cache of the CPU. The approach further includes marking the copied cache lines as transactional, processing the instruction to create a persistent log within non-volatile memory, and unmarking the copied cache lines from transactional, to non-transactional.
1. A method of atomically executing computer instructions by a central processing unit (CPU) of a computing device comprising non-volatile memory, the CPU configured to implement hardware transactional memory (HTM), the method comprising:
reading an instruction within a section of code designated as an HTM transaction;
copying at least one cache line from the non-volatile memory into a cache of the CPU, based on the instruction;
marking the copied at least one cache line as transactional;
creating a persistent log within the non-volatile memory, based on the instruction, by at least one of:
(1) based on the instruction being a log write instruction, converting the instruction to a non-temporal log write instruction, and executing the non-temporal log write instruction;
(2) based on the instruction being a write instruction, executing a non-temporal log write for data modified by the write instruction;
(3) based on the instruction being a custom log write instruction, executing a non-temporal write of a log entry; or
(4) based on the instruction being a log entry flush instruction, executing the log entry flush instruction; and
unmarking the copied at least one cache line from transactional, to non-transactional.
2. The method of claim 1 , wherein creating the persistent log comprises: based on the instruction being a log write instruction, converting the instruction to the non-temporal log write instruction, and executing the non-temporal log write instruction.
3. The method of claim 1 , wherein creating the persistent log comprises: based on the instruction being a write instruction, executing the non-temporal log write for data modified by the write instruction.
4. The method of claim 1 , wherein creating the persistent log comprises: based on the instruction being a custom log write instruction, executing the non-temporal write of a log entry.
5. The method of claim 1 , wherein creating the persistent log comprises: based on the instruction being a log entry flush instruction, executing the log entry flush instruction.
6. The method of claim 1 , wherein the cache is a private cache to the CPU such that the cache is inaccessible to other CPUs of the computing device.
7. The method of claim 1 , wherein subsequent to the unmarking, the CPU writes a COMMIT flag to the persistent log indicating to a recovery module that all log entries within the HTM transaction required to maintain consistency have been recorded to the non-volatile memory.
8. A non-transitory computer-readable storage medium comprising instructions, which when executed by a computing device, causes the computing device to carry out operations for atomically executing computer instructions by a central processing unit (CPU) of the computing device comprising non-volatile memory, the CPU configured to implement hardware transactional memory (HTM), comprising:
reading an instruction within a section of code designated as an HTM transaction;
copying at least one cache line from the non-volatile memory into a cache of the CPU, based on the instruction;
marking the copied at least one cache line as transactional;
creating a persistent log within the non-volatile memory, based on the instruction, by at least one of:
(1) based on the instruction being a log write instruction, converting the instruction to a non-temporal log write instruction, and executing the non-temporal log write instruction;
(2) based on the instruction being a write instruction, executing a non-temporal log write for data modified by the write instruction;
(3) based on the instruction being a custom log write instruction, executing a non-temporal write of a log entry; or
(4) based on the instruction being a log entry flush instruction, executing the log entry flush instruction; and
unmarking the copied at least one cache line from transactional, to non-transactional.
9. The non-transitory computer-readable storage medium of claim 8 , wherein creating the persistent log comprises: based on the instruction being a log write instruction, converting the instruction to the non-temporal log write instruction, and executing the non-temporal log write instruction.
10. The non-transitory computer-readable storage medium of claim 8 , wherein creating the persistent log comprises: based on the instruction being a write instruction, executing the non-temporal log write for data modified by the write instruction.
11. The non-transitory computer-readable storage medium of claim 8 , wherein creating the persistent log comprises: based on the instruction being a custom log write instruction, executing the non-temporal write of a log entry.
12. The non-transitory computer-readable storage medium of claim 8 , wherein creating the persistent log comprises: based on the instruction being a log entry flush instruction, executing the log entry flush instruction.
13. The non-transitory computer-readable storage medium of claim 8 , wherein the cache is a private cache to the CPU such that the cache is inaccessible to other CPUs of the computing device.
14. The non-transitory computer-readable storage medium of claim 8 , wherein subsequent to the unmarking, the CPU writes a COMMIT flag to the persistent log indicating to a recovery module that all log entries within the HTM transaction required to maintain consistency have been recorded to the non-volatile memory.
15. A computing device, comprising:
a CPU configured to implement hardware transactional memory (HTM);
a non-volatile memory;
a cache of the CPU;
wherein the computing device is configured to:
read an instruction within a section of code designated as an HTM transaction;
copy at least one cache line from the non-volatile memory into the cache, based on the instruction;
mark the copied at least one cache line as transactional;
create a persistent log within the non-volatile memory, based on the instruction, by at least one of:
(1) based on the instruction being a log write instruction, converting the instruction to a non-temporal log write instruction, and executing the non-temporal log write instruction;
(2) based on the instruction being a write instruction, executing a non-temporal log write for data modified by the write instruction;
(3) based on the instruction being a custom log write instruction, executing a non-temporal write of a log entry; or
(4) based on the instruction being a log entry flush instruction, executing the log entry flush instruction; and
unmark the copied at least one cache line from transactional, to non-transactional.
16. The computing device of claim 15 , wherein creating the persistent log comprises: based on the instruction being a log write instruction, converting the instruction to the non-temporal log write instruction, and executing the non-temporal log write instruction.
17. The computing device of claim 15 , wherein creating the persistent log comprises: based on the instruction being a write instruction, executing the non-temporal log write for data modified by the write instruction.
18. The computing device of claim 15 , wherein creating the persistent log comprises: based on the instruction being a custom log write instruction, executing the non-temporal write of a log entry.
19. The computing device of claim 15 , wherein creating the persistent log comprises: based on the instruction being a log entry flush instruction, executing the log entry flush instruction.
20. The computing device of claim 15 , wherein the cache is a private cache to the CPU such that the cache is inaccessible to other CPUs of the computing device.