System, apparatus, and method for optimizing a scalable GPU virtualization
Described herein is a method for optimizing a scalable GPU virtualization, comprising: providing each vGPU with a private shadow graphics translation table (GTT); copying vGPU's private shadow GTT to physical GTT along with the context switch, wherein the private shadow GTT allows vGPUs to share an overlapped range of a global graphics memory space.
1. A method for optimizing a scalable GPU virtualization, comprising:
providing each vGPU of one or more vGPUs with a private shadow graphics translation table (GTT);
copying vGPU's private shadow GTT, along with a context switch, to a physical GTT wherein the private shadow GTT allows the one or more vGPUs to share an overlapped range of a global graphics memory space, wherein the global graphics memory space comprises a low global graphics memory space and a high global graphics memory space; and
dividing the high global graphics memory space into a plurality of first-slots with each vGPU occupying a number of adjacent first-slots, the number of adjacent first-slots occupying less than a total of the high global graphics memory space.
2. The method of claim 1 , further comprising:
sharing the low global graphics memory space among all of the vGPUs by using ladder mapping and a fence memory space pool;
dividing the high global graphics memory space into a plurality of second-slots;
deploying one or more vGPUs in one second-slot.
3. The method of claim 2 , further comprising:
predicting a next vGPU that will run in a next time slice;
if adjacent vGPUs in a scheduling sequence are not deployed on a same second-slot, copying a next vGPU's Shadow GTT to its corresponding second-slot while a previous vGPU still occupies GPU to shorten a context switch time.
4. The method of claim 2 , further comprising:
arranging a context switch sequence of vGPUs on multiple second-slots.
5. The method of claim 4 , wherein arranging the context switch sequence of the vGPUs on the multiple second-slots further comprises:
finding a slot k with a maximum number of vGPUs;
alternately poping the vGPUs from the slot k and other slots; and
inserting the vGPUs into an OutputVmList which indicates a scheduling sequence of a single round.
6. The method of claim 5 , wherein arranging the context switch sequence of the vGPUs on the multiple slots further comprises:
if the slot k firstly pops out all of its vGPUs, returning to the step of finding the slot k with the maximum number of vGPUs to determine the scheduling sequence of the vGPUs on other slots; and
if all the other slots firstly pop out their vGPUs while some vGPUs in the slot k are not popped out, inserting all remaining virtual machines (VMs) in the slot k into the OutputVmList.
7. The method of claim 1 , further comprising:
non-conducting the context switch for idle vGPU instances; and
non-copying entries from idle vGPU's private shadow GTT to the physical GTT.
8. The method of claim 1 , wherein the one or more vGPUs includes: a first vGPU occupying first-slots 1 to 5, and a second vGPU occupying first-slots 4 to 6.
9. An apparatus for optimizing a scalable GPU virtualization, comprising:
one or more guest vGPUs, each having a private shadow graphics translation table (GTT) to allow the one or more guest vGPUs to share an overlapped range of a global graphics memory space, wherein the global graphics memory space comprises a low global graphics memory space and a high global graphics memory space; and
a host vGPU having:
a ladder mapping unit, configured to allow CPU directly access host memory space serving the graphics memory, which bypasses the global graphics memory space, to share the low global graphics memory space among all of the vGPUs;
a fence memory space pool, the fence memory space pool being a dedicated part of the low global graphics memory to work for fence registers, to address malfunction of fence registers;
a fine-grained slotting unit, configured to divide the high global graphics memory space into a plurality of first-slots with each vGPU occupying a number of adjacent first-slots, the number of adjacent first-slots occupying less than a total of the high global graphics memory space; and
a slot sharing unit, configured to divide the high global graphics memory space into a plurality of second-slots and deploy one or more vGPUs in one second-slot.
10. The apparatus of claim 9 , wherein the one or more guest vGPUs includes: a first vGPU occupying first-slots 1 to 5, and a second vGPU occupying first-slots 4 to 6.
11. The apparatus of claim 9 , wherein the host vGPU further comprises:
a predictive GTT copy unit, configured to predict a next vGPU that will run in a next time slice, wherein:
if adjacent vGPUs in a scheduling sequence are not deployed on a same second-slot, a next vGPU's Shadow GTT is copied to its corresponding second-slot while a previous vGPU still occupies GPU to shorten a context switch time.
12. The apparatus of claim 9 , wherein the host vGPU further comprises:
a predictive-copy aware scheduling unit, configured to arrange a context switch sequence of vGPUs on multiple second-slots.
13. The apparatus of claim 12 , wherein the predictive-copy aware scheduling unit is further configured to:
find a slot k with a maximum number of vGPUs;
alternately pop the vGPUs from the slot k and other slots; and
insert the vGPUs into an OutputVmList which indicates a scheduling sequence of a single round.
14. The apparatus of claim 13 , wherein the predictive-copy aware scheduling unit is further configured to:
if the slot k firstly pops out all of its vGPUs, find again the slot k with the maximum number of vGPUs to determine the scheduling sequence of the vGPUs on other slots; and
if all the other slots firstly pop out their vGPUs while some vGPUs in the slot k are not popped out, insert all remaining virtual machines (VMs) in the slot k into the OutputVmList.