Static random access memory and method of controlling the same

1. A static random access memory (SRAM) comprising:

a memory cell, wherein the memory cell comprises at least two p-type pass gates;

a bit line connected to the memory cell;

a bit line bar connected to the memory cell;

a word line connected to the memory cell;

an n-type transistor connected between a ground voltage and a first node;

a first inverter having an input terminal configured to receive a data signal and an output terminal connected to the word line, the first inverter being connected between a supply voltage and the first node; and

a voltage control unit configured to control the N-type transistor and to control the memory cell by providing an operating voltage on the first node which affects operation of the first inverter and thereby causes a voltage on the word line to undergo at least a double transition including a first transition to the ground voltage and then a second transition to an intermediate voltage which is greater than the ground voltage but substantially lower than the supply voltage; and

wherein:

the voltage control unit includes a p-type capacitor-connected transistor connected to the first node and thereby to the word line; and

the voltage control unit is further configured to selectively adjust voltages correspondingly of the bit line and the bit line bar.

2. The SRAM of claim 1 , wherein each p-type pass gate of the at least two p-type pass gates has a three-dimensional gate structure.

3. The SRAM of claim 1 , wherein:

after the voltage on the word line undergoes the second transition from the ground voltage to the intermediate voltage, the voltage control unit is further configured to provide the operating voltage on the first node so as to further affect operation of the first inverter and thereby cause the voltage on the word line to undergo a third transition from the intermediate voltage to the ground voltage.

4. The SRAM of claim 1 , wherein the voltage control unit further includes:

series-connected inverters coupled between the p-type capacitor-connected transistor and a timing control unit.

5. The SRAM of claim 4 , wherein:

the voltage control unit is further configured to provide a signal on a second node between first and second ones of the series-connected inverters to a gate electrode of the N-type transistor.

6. The SRAM of claim 1 , wherein:

the memory cell is a single-port memory cell, a two-port memory cell or a dual-port memory cell.

7. A semiconductor device comprising:

a static random access memory (SRAM) comprising:

a memory cell, wherein the memory cell comprises at least two p-type pass gates;

a bit line connected to the memory cell;

a bit line bar connected to the memory cell;

a word line connected to the memory cell;

a word line driver including a first inverter having an input configured to receive a data signal and an output connected to the word line, the first inverter being connected between a supply voltage and an adjustment line;

a voltage adjuster including an n-type transistor connected between a ground voltage and the adjustment line; and

a voltage control unit connected to the memory cell, the voltage control unit being connected to the adjustment line and connected to the bit line by a second inverter and connected to the bit line bar by a third inverter, wherein the voltage control unit is configured to control the n-type transistor and to control the memory cell by providing an operating voltage on the adjustment line which affects operation of the first inverter and thereby causes a voltage on the word line to undergo at least a double transition including a first transition to the ground voltage and then a second transition to an intermediate voltage which is greater than the ground voltage but substantially lower than the supply voltage; and

wherein the voltage control unit includes a p-type capacitor-connected transistor connected to the adjustment line; and

the voltage control unit is further configured to selectively adjust voltages correspondingly of the bit line and the bit line bar.

8. The semiconductor device of claim 7 , wherein the memory cell is a single-port memory cell or a dual-port memory cell.

9. The semiconductor device of claim 7 , wherein the memory cell is a two-port memory cell.

10. The semiconductor device of claim 7 , wherein each p-type pass gate of the at least two p-type pass gates has a three-dimensional gate structure.

11. The semiconductor device of claim 7 , wherein:

an output of the second inverter is configured to drive only the bit line, and is coupled to the bit line, and

an output of the third inverter is configured to drive only the bit line bar, and is coupled to the bit line bar.

12. The semiconductor device of claim 7 , wherein:

after the voltage on the word line undergoes the second transition from the ground voltage to the intermediate voltage, the voltage control unit is further configured to provide the operating voltage on the adjustment line so as to further affect operation of the first inverter and thereby cause the voltage on the word line to undergo a third transition from the intermediate voltage to the ground voltage.

13. The semiconductor device of claim 7 , wherein the voltage control unit further includes:

series-connected inverters coupled between the p-type capacitor-connected transistor and a timing control unit.

14. The semiconductor device of claim 13 , wherein:

the voltage control unit is further configured to provide a signal on a node between first and second ones of the series-connected inverters to a gate electrode of the N-type transistor.

15. A method of controlling a static random access memory (SRAM), the method comprising:

pre-charging a word line to a reference voltage, wherein the word line is connected to a memory cell, wherein the memory cell comprises at least two p-type pass gates which connect the memory cell correspondingly to a bit line and a bit line bar;

activating a voltage control unit connected to the word line by a series connection of a p-type capacitor-connected transistor and a first inverter, the first inverter having an input terminal configured to receive a data signal and an output terminal connected to the word line, the first inverter being connected between a supply voltage and a first node;

wherein the activating the voltage control unit comprises:

outputting a first control signal from a second inverter included in the voltage control unit to a voltage adjuster, the voltage adjuster including an n-type transistor connected between a ground voltage and the first node; and

controlling the voltage adjuster in response to the first control signal, the controlling the voltage adjuster including:

selectively adjusting a first data signal on the bit line connected to the memory cell;

selectively adjusting a second data signal on the bit line bar connected to the memory cell; and

affecting operation of the first inverter and which thereby causes a voltage on the word line to undergo at least a double transition including a first transition to the ground voltage and then a second transition to an intermediate voltage which is greater than the ground voltage but substantially lower than the supply voltage.

16. The method of claim 15 , wherein:

after the voltage on the word line undergoes the second transition from the ground voltage to the intermediate voltage, the controlling the voltage adjuster further causes the voltage on the word line to undergo a third transition from the intermediate voltage to the ground voltage.

17. The method of claim 15 , wherein:

the voltage control unit further includes:

series-connected inverters coupled between the p-type capacitor-connected transistor and a timing control unit, the series-connected inverters including the second inverter; and

the activating a voltage control unit includes:

receiving a second control signal from the timing control unit; and

using the series-connected inverters to provide a delayed version of the second control signal as the first control signal.

18. The method of claim 15 , wherein:

the voltage control unit further includes:

series-connected inverters coupled between the p-type capacitor-connected transistor and a timing control unit, the series-connected inverters including the second inverter; and

the controlling the voltage adjuster further includes:

using the series-connected inverters to provide a delayed version of the control signal to a gate electrode of the N-type transistor as the first control signal.

19. The method of claim 18 , wherein the using the series-connected inverters to provide a delayed version of the control signal to a gate electrode of the N-type transistor includes:

using a signal on a second node between first and second ones of the series-connected inverters as the delayed version of the control signal.

20. The method of claim 15 , wherein:

the memory cell is a single-port memory cell, a two-port memory cell or a dual-port memory cell.