IP Library › Granted Patent US 10,431,436
Granted Patent B2
US 10,431,436 · App. 15/690,414 · Granted Oct 1, 2019

Method and system of monitoring and controlling deformation of a wafer substrate

Inventors: Huma Ashraf (Newport, GB); Kevin Riddell (Abergavenny, GB); Roland Mumford (Cardiff, GB); Grant Baldwin (Newport, GB)
Assignee: SPTS TECHNOLOGIES LIMITED
H01J37/32935H01J37/32082H01J37/32715H01J37/32724H01J37/32917H01L21/67069H01L21/67288H01J2237/334
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Quick Facts
Patent No.
US 10,431,436
App. No.
15/690,414
Granted
Oct 1, 2019
Kind
B2
Abstract

A method and system are for monitoring and controlling deformation of a wafer substrate during a plasma etching of the wafer substrate. The method includes disposing a wafer substrate on a platen assembly within a process chamber so that an entire upper surface of the wafer is exposed, passing a process gas into the process chamber, applying a radio frequency bias voltage to the platen assembly, generating a plasma within the process chamber, monitoring a voltage difference between the platen assembly and the process chamber, during the etch process, and attenuating or extinguishing the plasma to prevent further etching once a threshold monitored voltage is reached.

Claims (20)

1. A method of monitoring and controlling deformation of an electrically insulating wafer substrate during plasma etching of the wafer substrate, the method comprising:

disposing an electrically insulating wafer substrate on a platen assembly within a process chamber so that an entire upper surface of the electrically insulating wafer substrate is exposed;

passing a process gas into the process chamber;

applying a radio frequency bias voltage to the platen assembly;

etching the exposed entire upper surface of the electrically insulating wafer substrate by generating a plasma within the process chamber;

determining, during said etching, a warping of the electrically insulating wafer substrate relative to the platen assembly by monitoring a voltage difference between the platen assembly and the process chamber;

attenuating or extinguishing the plasma to prevent further etching once a threshold monitored voltage is reached.

2. A method according to claim 1 , further comprising controlling a temperature of the platen assembly, to regulate a temperature of the wafer substrate.

3. A method according to claim 1 , wherein the insulating wafer substrate is a sapphire substrate.

4. A method according to claim 1 , wherein the insulating wafer substrate is a glass substrate.

5. A method according to claim 1 , wherein the plasma is generated by inductively or capacitively coupling radio frequency (RF) power into the process chamber.

6. A method according to claim 5 , further comprising inductively coupling RF power into the process chamber by applying an RF potential to one or more antenna disposed around the process chamber.

7. A method according to claim 1 , comprising a monitoring a peak-to-peak voltage difference (Vpp) between the platen assembly and the process chamber.

8. A method according to claim 7 , further comprising attenuating or extinguishing the plasma, once the Vpp between the platen assembly and the process chamber exceeds 10% of Vpp at the start of said etching.

9. A method according to claim 7 , further comprising attenuating or extinguishing the plasma, once the Vpp between the platen assembly and the process chamber exceeds 20% of the Vpp at the start of said etching.

10. A method according to claim 7 , further comprising attenuating or extinguishing the plasma once the Vpp reduces to a predetermined value which is characteristic of a Vpp of a representative insulating wafer substrate which extends in a substantially flat orientation upon the platen assembly.

11. A method according to claim 1 , comprising or further comprising monitoring a direct current voltage difference (Vdc) between the platen assembly and the process chamber.

12. A method according to claim 11 , further comprising attenuating or extinguishing the plasma, once the Vdc between the platen assembly and the process chamber exceeds 50% of the Vdc at the start of said etching.

13. A method according to claim 11 , further comprising attenuating or extinguishing the plasma, once the Vdc between the platen assembly and the process chamber exceeds 100% of the Vdc at the start of said etching process.

14. A method according to claim 11 , further comprising attenuating or extinguishing the plasma once the Vdc reduces to a predetermined value which is characteristic of a Vdc of a representative insulating wafer substrate which extends in a substantially flat orientation upon the platen assembly.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 6, 2017
From: ASHRAF, HUMA; RIDDELL, KEVIN; MUMFORD, ROLAND; BALDWIN, GRANT
To: SPTS TECHNOLOGIES LIMITED
Reel/Frame 043494/0086 →
Priority Claims (1)
GB 1615114.4 · Sep 6, 2016 · national
Continuity (1)
Related Publication 20180144911A1 · May 24, 2018