Semiconductor device having contact plugs
A semiconductor device including a first fin active area substantially parallel to a second fin active area, a first source/drain in the first fin active area, a second source/drain in the second fin active area, a first contact plug on the first source/drain, and a second contact plug on the second source/drain. The center of the second contact plug is offset from the center of the second source/drain.
1. A semiconductor device, comprising:
a substrate;
a first fin on the substrate;
a first source/drain on the first fin; and
a first contact plug on the first source/drain,
wherein a center of the first contact plug is offset from a center of the first fin,
wherein a bottom surface of the first contact plug is inclined with respect to a top surface of the substrate,
wherein the bottom surface of the first contact plug includes a first edge and a second edge opposite to the first edge, and
wherein the first edge is at a different level than the second edge.
2. The semiconductor device of claim 1 , wherein the first fin has a line shape or a bar shape.
3. The semiconductor device of claim 1 , further comprising a gate electrode crossing the first fin.
4. The semiconductor device of claim 1 , wherein the first contact plug has a first sidewall and a second sidewall opposite to the first sidewall, and
wherein a length of the second sidewall is greater than a length of the first sidewall.
5. The semiconductor device of claim 4 , further comprising:
a second fin on the substrate, the second fin being immediately adjacent to the first fin and substantially parallel to the first fin;
a second source/drain on the second fin; and
a second contact plug on the second source/drain,
wherein a center of the second contact plug is offset from a center of the second fin, and
wherein a bottom surface of the second contact plug is inclined with respect to the top surface of the substrate.
6. The semiconductor device of claim 5 , wherein the second contact plug has a third sidewall and a fourth sidewall opposite to the third sidewall, and wherein a length of the third sidewall is greater than a length of the fourth sidewall.
7. The semiconductor device of claim 6 , wherein the second and third sidewalls are positioned between the first and fourth sidewalls.
8. The semiconductor device of claim 5 , wherein a distance between the bottom surface of the first contact plug and the top surface of the substrate decreases as a distance between the bottom surface of the first contact plug and the second fin decreases.
9. The semiconductor device of claim 5 , wherein a distance between the bottom surface of the second contact plug and the top surface of the substrate decreases as a distance between the bottom surface of the second contact plug and the first fin decreases.
10. A semiconductor device, comprising:
a substrate;
a first fin on the substrate;
a first source/drain on the first fin; and
a first contact plug on the first source/drain,
wherein a center of the first contact plug is offset from a center of the first fin,
wherein the first contact plug has a first sidewall and a second sidewall opposite to the first sidewall, and
wherein a lowermost point of the first sidewall is at a different level than a lowermost point of the second sidewall.
11. The semiconductor device of claim 10 , wherein the first fin has a line shape or a bar shape.
12. The semiconductor device of claim 10 , further comprising a gate electrode crossing the first fin.
13. The semiconductor device of claim 10 , further comprising:
a second fin on the substrate, the second fin being immediately adjacent to the first fin and substantially parallel to the first fin;
a second source/drain on the second fin; and
a second contact plug on the second source/drain,
wherein a center of the second contact plug is offset from a center of the second fin,
wherein the second contact plug has a third sidewall and a fourth sidewall opposite to the third sidewall, and
wherein a lowermost point of the third sidewall is at a different level than a lowermost point of the fourth sidewall.
14. The semiconductor device of claim 13 , wherein the second and third sidewalls are positioned between the first and fourth sidewalls.
15. The semiconductor device of claim 13 , wherein a distance between a bottom surface of the first contact plug and a top surface of the substrate decreases as a distance between the bottom surface of the first contact plug and the second fin decreases.
16. The semiconductor device of claim 13 , wherein a distance between a bottom surface of the second contact plug and a top surface of the substrate decreases as a distance between the bottom surface of the second contact plug and the first fin decreases.
17. A semiconductor device, comprising:
a substrate;
a first fin on the substrate;
a second fin on the substrate, the second fin being immediately adjacent to the first fin and substantially parallel to the first fin;
a device isolation layer between the first and second fins;
a first source/drain on the first fin; and
a first contact plug on the first source/drain,
wherein a center of the first contact plug is between a center of the first fin and a center of the device isolation layer, and
wherein a bottom surface of the first contact plug is inclined with respect to a top surface of the substrate.
18. The semiconductor device of claim 17 , further comprising a second source/drain on the second fin,
wherein a center of a second contact plug is between a center of the second fin and the center of the device isolation layer, and
wherein a bottom surface of the second contact plug is inclined with respect to the top surface of the substrate.
19. The semiconductor device of claim 17 , wherein the first source/drain include SiGe or Si formed by a selective epitaxial growth method.
20. The semiconductor device of claim 17 , wherein an integrated circuit of the semiconductor device constitutes an SRAM.