Three-dimensional semiconductor memory devices

1. A three-dimensional semiconductor memory device, comprising:

a substrate; and

a first channel group, a second channel group, a third channel group, and a fourth channel group each arranged in a first direction on the substrate,

the first channel group to the fourth channel group being spaced apart from each other along a second direction on the substrate that crosses the first direction,

each of the first channel group, the second channel group, the third channel group, and the fourth channel group including a plurality of vertical channels that extend in a third direction perpendicular to a top surface of the substrate,

the first channel group and the second channel group being adjacent to each other in the second direction and spaced apart by a first distance in the second direction,

the second channel group and the third channel group being adjacent to each other in the second direction and spaced apart by a second distance less than the first distance in the second direction, and

the third channel group and the fourth channel group being adjacent to each other in the second direction and spaced apart by a third distance less than the second distance in the second direction.

2. The device of claim 1 , further comprising:

a first electrode structure, a second electrode structure, a third electrode structure, and a fourth electrode structure that extend along the first direction and are spaced apart from each other along the second direction, wherein

each of the first electrode structure, the second electrode structure, the third electrode structure, and the fourth electrode structure include a plurality of electrodes stacked on top of each other along the third direction, and

the vertical channels of the first channel group, the second channel group, the third channel group, and the fourth channel group penetrate the first electrode structure, the second electrode structure, the third electrode structure, and the fourth electrode structure, respectively.

3. The device of claim 1 , wherein

the vertical channels include first vertical channels, second vertical channels, third vertical channels and fourth vertical channels sequentially arranged along the second direction,

lower portions of the first vertical channels, the second vertical channels, the third vertical channels, and the fourth vertical channels are spaced apart from each other by a first lower distance, and

upper portions of the first vertical channels and the second vertical channels are spaced apart by a first upper distance,

upper portions of the second vertical channels and the third vertical channels are spaced apart by a second upper distance less than the first upper distance, and

the first upper distance and the second upper distance are less than the first lower distance.

4. The device of claim 1 , further comprising:

a plurality of fourth channel groups, wherein

the substrate includes a first edge region, a second edge region, and a central region between the first edge region and the second edge region,

the first channel group and the second channel group are provided on each of the first edge region and the second edge region, and

the plurality of fourth channel groups include the fourth channel group and are on the central region,

the plurality of fourth channel groups are spaced apart from each other at a fourth distance less than the second distance.

5. The device of claim 1 , further comprising:

an electrode structure on the substrate, wherein

the electrode structure extends along the second direction on the substrate,

the electrode structure includes a plurality of electrodes stacked along the third direction, and

the vertical channels of the first channel group, the second channel group, the third channel group, and the fourth channel group commonly penetrate the electrode structure.

6. The device of claim 1 , further comprising:

an upper electrode structure on the substrate, wherein ; and

a first upper channel group, a second upper channel group, a third upper channel group, and a fourth upper channel group respectively on the first channel group, the second channel group, the third channel group, and the fourth channel group, each of the first upper channel group to the fourth upper channel group including a plurality of upper channels that penetrate the upper electrode structure,

wherein the first upper channel group and the second upper channel group are adjacent to each other in the second direction and are spaced apart at a third distance less than the first distance.

7. A three-dimensional semiconductor memory device, comprising:

a substrate;

a lower electrode structure on the substrate, the lower electrode structure including a plurality of lower electrodes that are vertically stacked on the substrate;

a plurality of lower vertical channels that penetrate the lower electrode structure;

an upper electrode structure on the lower electrode structure, the upper electrode structure including a plurality of upper electrodes that are vertically stacked on the lower electrode structure; and

a plurality of upper vertical channels that penetrate the upper electrode structure and are connected to the plurality of lower vertical channels,

a first distance between upper portions of the plurality of lower vertical channels that neighbor each other is different from a second distance between upper portions of the plurality of upper vertical channels that neighbor each other.

8. The device of claim 7 , wherein the second distance is less than the first distance.

9. The device of claim 7 , wherein a distance between lower portions of adjacent ones of the plurality of upper vertical channels is substantially the same as the first distance.

10. The device of claim 7 , wherein an upper width of the plurality of lower vertical channels is greater than an upper width of the plurality of upper vertical channels.

11. The device of claim 7 , wherein each of the plurality of lower vertical channels and the plurality of upper vertical channels has a lower width less than an upper width.

12. The device of claim 7 , wherein

each of the lower electrode structure and the upper electrode structure has a first sidewall perpendicular to the substrate,

the plurality of lower vertical channels include a first lower vertical channel that is spaced apart from the first sidewall of the lower electrode structure at a first horizontal distance, and

the plurality of upper vertical channels include a first upper vertical channel that is spaced apart from the first sidewall of the upper electrode structure at a second horizontal distance different from the first horizontal distance, and

the first upper vertical channel is connected to the first lower vertical channel.

13. The device of claim 7 , wherein a number of the plurality of lower electrodes is different from a number of the plurality of upper electrodes.

14. The device of claim 7 , further comprising:

a connection pad between the plurality of lower vertical channels and the plurality of upper vertical channels, wherein

an uppermost lower electrode of the plurality of lower electrodes surrounds the connection pad.

15. A three-dimensional semiconductor memory device, comprising:

a substrate;

a first lower channel group and a second lower channel group on the substrate, the first lower channel group and the second lower channel group each including a plurality of lower vertical channels on the substrate, the first lower channel group and the second lower channel group being spaced apart at a first distance; and

a first upper channel group and a second upper channel group on the substrate at a height above a height of the first lower channel group and a height of the second lower channel group, the first upper channel group and the second upper channel group each including a plurality of upper vertical channels correspondingly connected to the lower vertical channels, the first upper channel group and the second upper channel group being spaced apart at a second distance that is less than the first distance.

16. The device of claim 15 , wherein

the upper vertical channels of the first upper channel group are vertically aligned with the lower vertical channels of the first lower channel group, and

the upper vertical channels of the second upper channel group are vertically misaligned with the lower vertical channels of the second lower channel group.

17. The device of claim 15 , wherein

upper portions of the lower vertical channels of the first lower channel group are spaced apart at a first upper distance, and

upper portions of the upper vertical channels of the first upper channel group are spaced apart at a second upper distance that is less than the first upper distance.

18. The device of claim 15 , wherein the lower vertical channels and the upper vertical channels have substantially a same width.

19. The device of claim 15 , further comprising:

a first lower electrode structure and a second lower electrode structure spaced apart from each other on the substrate; and

a first upper electrode structure and a second upper electrode structure on the first lower electrode structure and the second lower electrode structure, respectively, wherein

each of the first lower electrode structure and the second lower electrode structure includes a plurality of vertically stacked lower electrodes,

each of the first upper electrode structure and the second upper electrode structure includes a plurality of vertically stacked upper electrodes, and

the first lower electrode structure and the second lower electrode structure have substantially a same width.