Transistor structure
A transistor structure including a substrate, a transistor device, a split buried layer, and a second buried layer is provided. The substrate has a device region. The transistor device is located in the device region. The split buried layer is located under the transistor device in the substrate and includes first buried layers separated from each other. The second buried layer is located under the split buried layer in the substrate and connects the first buried layers. The second buried layer and the split buried layer have a first conductive type. The transistor structure may have a higher breakdown voltage.
1. A transistor structure, comprising:
a substrate, having a device region;
a transistor device, located in the device region;
a split buried layer, located under the transistor device in the substrate and comprising at least three first buried layers separated from each other; and
a second buried layer, located under the split buried layer in the substrate and connecting the first buried layers, wherein the second buried layer and the split buried layer have a first conductive type.
2. The transistor structure as claimed in claim 1 , wherein the split buried layer and the second buried layer form a stepped structure at a position in which the second buried layer and the split buried layer are connected.
3. The transistor structure as claimed in claim 1 , wherein a portion of the second buried layer overlapping the split buried layer does not exceed two ends of the split buried layer.
4. The transistor structure as claimed in claim 1 , wherein the substrate comprises:
a semiconductor substrate; and
a semiconductor layer, disposed on the semiconductor substrate.
5. The transistor structure as claimed in claim 4 , wherein the semiconductor substrate and the semiconductor layer have a second conductive type.
6. The transistor structure as claimed in claim 4 , wherein the semiconductor layer comprises an epitaxial silicon layer.
7. The transistor structure as claimed in claim 4 , wherein the split buried layer is located between the semiconductor substrate and the semiconductor layer.
8. The transistor structure as claimed in claim 1 , further comprising:
a first well region, located at one side of the transistor device in the substrate and connected to the split buried layer, wherein the first well region has the first conductive type.
9. The transistor structure as claimed in claim 8 , wherein the split buried layer, the second buried layer, and the first well region surround the transistor device.
10. The transistor structure as claimed in claim 8 , further comprising:
a second well region, located in the first well region and has the first conductive type.
11. The transistor structure as claimed in claim 10 , further comprising:
a first doped region, located in the second well region and having the first conductive type.
12. The transistor structure as claimed in claim 8 , further comprising:
a first isolation structure, disposed in the substrate and located between the first well region and the transistor device.
13. The transistor structure as claimed in claim 1 , wherein the transistor device comprises:
a gate structure, disposed on the substrate;
a second doped region and a third doped region, respectively located at one side and the other side of the gate structure in the substrate and having a second conductive type; and
a fourth doped region, located at one side of the second doped region away from the gate structure in the substrate and having the first conductive type.
14. The transistor structure as claimed in claim 13 , wherein the transistor device further comprises:
a body region, located at one side of the gate structure in the substrate and having the first conductive type, wherein the second doped region and the fourth doped region are located in the body region; and
a drift region, located at the other side of the gate structure in the substrate and having the second conductive type, wherein the third doped region is located in the drift region.
15. The transistor structure as claimed in claim 14 , wherein the transistor device is mirror symmetric relative to an axis penetrating through the body region along a normal direction of the substrate.
16. The transistor structure as claimed in claim 14 , wherein the transistor device further comprises:
a third well region, located in the substrate and having the second conductive type, wherein the body region and the drift region are located in the third well region.
17. The transistor structure as claimed in claim 13 , wherein the transistor device further comprises:
a second isolation structure, disposed in the substrate and located between the second doped region and the third doped region.
18. The transistor structure as claimed in claim 17 , wherein a portion of the gate structure is located on the second isolation structure.
19. The transistor structure as claimed in claim 1 , wherein the transistor device comprises a lateral diffused metal-oxide-semiconductor transistor or a drain extended metal-oxide-semiconductor transistor.
20. A transistor structure, comprising:
a substrate, having a device region;
a transistor device, located in the device region;
a split buried layer, located under the transistor device in the substrate and comprising at least three first buried layers separated from each other, wherein the split buried layer has an opening between adjacent two first buried layers; and
a second buried layer, located under the split buried layer in the substrate and sealing a bottom portion of the opening, wherein the second buried layer and the split buried layer have a first conductive type.