High electron mobility transistors with localized sub-fin isolation
Crystalline heterostructures including an elevated fin structure extending from a sub-fin structure over a substrate. Devices, such as III-V transistors, may be formed on the raised fin structures while silicon-based devices (e.g., transistors) may be formed in other regions of the silicon substrate. A sub-fin isolation material localized to a transistor channel region of the fin structure may reduce source-to-drain leakage through the sub-fin, improving electrical isolation between source and drain ends of the fin structure. Subsequent to heteroepitaxially forming the fin structure, a portion of the sub-fin may be laterally etched to undercut the fin. The undercut is backfilled with sub-fin isolation material. A gate stack is formed over the fin. Formation of the sub-fin isolation material may be integrated into a self-aligned gate stack replacement process.
1. A field effect transistor (FET), comprising:
a sub-fin structure comprising:
a fin of a first crystalline material over a surface of a substrate comprising a second crystalline material and surrounded by a dielectric trench material; and a sub-fin isolation material, wherein the sub-fin isolation material is amorphous and extends through at least a portion of the first crystalline material, wherein the sub-fin isolation material has a first lateral dimension orthogonal to a longest length of the fin of the first crystalline material, and the first lateral dimension is larger than a width of the fin of the first crystalline material;
a fin structure comprising a third crystalline material and including a source and a drain on opposite ends of a channel region, the fin structure extending from the sub-fin structure with the channel region separated from the first crystalline material by the sub-fin isolation material;
a gate electrode stack over the channel region, wherein at least a gate electrode of the gate electrode stack has a second lateral dimension orthogonal to the longest length of the fin structure that is larger than the width of the fin structure, and a portion of the gate electrode stack extends over the sub-fin isolation material beyond an edge of the fin structure;
a source contact coupled to the source; and
a drain contact coupled to the drain.
2. The transistor of claim 1 , wherein the sub-fin isolation material has a lateral dimension parallel to a source-drain length of the fin structure that is larger than a length of the channel region covered by the gate electrode stack.
3. The transistor of claim 2 , wherein the sub-fin isolation material occupies a recess in the first crystalline material, the recess having one or more crystallographic facets in the first crystalline material.
4. The transistor of claim 1 , wherein:
the sub-fin structure comprises a fin of the first crystalline material that is over the substrate and is surrounded by a dielectric trench material that is over the surface of the substrate; and
the sub-fin isolation material has a first lateral dimension orthogonal to a longest length of the fin of the first crystalline material that is equal to a width of the fin of the first crystalline material, and has a second lateral dimension parallel to the longest length of the fin of the first crystalline material that is at least equal to a length of the gate electrode stack that is over the channel region.
5. The transistor of claim 1 , wherein:
the first and second lateral dimensions are equal with a first sidewall of the gate electrode stack aligned with a second sidewall of the sub-fin isolation material that interfaces with the trench material.
6. The transistor of claim 1 , wherein the sub-fin isolation material has a greater thickness within a region below the fin structure than in a region extending beyond sidewalls of the fin structure.
7. The transistor of claim 1 , wherein the gate stack comprises a gate electrode and a gate dielectric material, and the gate dielectric material is between the gate electrode and a portion of the sub-fin isolation material that extends beyond sidewalls of the fin structure.
8. The transistor of claim 1 , wherein:
the fin structure further comprises a fourth crystalline material between the third and first crystalline materials;
the fourth crystalline material is in contact with the first crystalline material at the source and drain and is in contact with the sub-fin isolation material within the channel region.
9. The transistor of claim 1 , wherein:
the first crystalline material comprises a first III-V material;
the second crystalline material comprises silicon; and
the third crystalline material comprises a second III-V material;
the sub-fin structure comprises a fin of the first crystalline material that is over the second crystalline material and is located within a trench that extends through a dielectric trench material, which is also over the second crystalline material; and
the sub-fin isolation material is embedded within the trench material.
10. The transistor of claim 1 , wherein the source and the drain further comprise a semiconductor material comprising impurity dopants, wherein the semiconductor material comprising impurity dopants is in contact with the contact metallization and is on a sidewall of the fin structure.
11. The transistor of claim 1 , wherein:
the first crystalline material comprises a first alloy of: GaAs; InP; InAs; InGaAs; AlGaAs; GaP; AlAs; or InGaP;
the second crystalline material comprises Si;
the third crystalline material comprises a second alloy of: GaAs; InP; InAs; InGaAs; AlGaAs; GaP; AlAs; or InGaP; and
the sub-fin isolation material comprises a metal oxide, a silicon oxide, or a polymer dielectric.
12. A microelectronic device, comprising:
a plurality of sub-fin structures over a crystalline substrate, each sub-fin structure comprising a fin of a first crystalline III-V material and the crystalline substrate comprising silicon;
a plurality of fin structures aligned with the sub-fin structures, each fin structure comprising a second crystalline III-V material and coupled to a source and drain on opposite ends of a channel region, wherein the second crystalline III-V material of one fin structure is in contact with the first crystalline III-V material of one sub-fin structure at the source or drain;
an amorphous sub-fin isolation material stripe intersecting the plurality of sub-fin structures and fin structures, wherein the sub-fin isolation material stripe separates the second crystalline III-V material of each fin structure from the first crystalline III-V material at the channel regions;
a gate electrode stack stripe over the sub-fin isolation material stripe, wherein the gate electrode stack comprises at least a gate dielectric material and an overlying gate metal, and wherein the gate electrode stack stripe is over the channel region and in contact with a sidewall of each of the fin structures; and
contact metallization on opposite sides of the gate electrode stack stripe and coupled to the source and drain.
13. The device of claim 12 , wherein sub-fin isolation material stripe contacts the crystalline substrate within a region where the sub-fin isolation material stripe intersects the fin structure.
14. The device of claim 12 , wherein the fin structure further comprises a third crystalline III-V material over the second crystalline III-V material, and the gate dielectric material is in contact with a sidewall of third crystalline III-V material with the channel region.
15. A method of forming a field effect transistor, the method comprising:
receiving a fin comprising a first III-V material on a sub-fin comprising a second III-V material;
removing a width of the sub-fin to undercut the fin within a channel region of the fin, wherein the removing comprises:
forming a gate stack mandrel over the channel region of the fin and a mask material over the ends of the fin adjacent to the gate stack mandrel;
removing the gate stack mandrel while retaining the mask material; and
etching the sub-fin while the ends of the fin are protected by the mask material;
backfilling the undercut fin channel region with a sub-fin isolation material;
forming a gate stack over the channel region of the fin; and
forming a source and a drain coupled to the channel region of the fin.
16. The method of claim 15 , further comprising:
forming a trench in a trench material, the trench exposing a crystalline substrate surface;
heteroepitaxially growing the sub-fin on an exposed substrate surface within the trench; and
heteroepitaxially growing the fin on a sub-fin surface within the trench.
17. The method of claim 15 , wherein forming the gate stack mandrel further comprises depositing a mandrel material over a sidewall of the fin and a portion of a sidewall of the sub-fin.
18. The method of claim 15 , wherein isotropically etching the sub-fin further comprises forming etch facets in the sub-fin by exposing the sub-fin to a crystallographic etchant.
19. The method of claim 16 , wherein backfilling the undercut fin channel region with the sub-fin isolation material further comprises at least one of:
spinning on a polymer dielectric;
depositing a metal oxide with an atomic layer deposition process; or
depositing a silicon oxide with a chemical vapor deposition and reflow process.
20. The method of claim 15 , wherein forming the gate stack over the channel region of the fin further comprises:
planarizing the sub-fin isolation material;
recessing the sub-fin isolation material to expose sidewalls of the fin while the ends of the fin are protected by the mask material;
depositing a gate dielectric material and a gate metal over the recessed sub-fin isolation material and over the exposed fin sidewalls; and
planarizing the gate metal with the mask material.