Data processing device and data processing method using low density parity check encoding for decreasing signal-to-noise power ratio

1. A transmitting device for generating a digital television broadcast signal and for decreasing a signal-to-noise power ratio of the generated digital television broadcast signal, the transmitting device comprising:

circuitry configured to

receive data to be transmitted in a digital television broadcast signal;

perform low density parity check (LDPC) encoding on input bits of the received data according to a parity check matrix of an LDPC code having a code length of 16200 bits and a code rate of 12/15 to generate an LDPC code word, the LDPC code enabling error correction processing to correct errors generated in a transmission path of the digital television broadcast signal,

wherein the LDPC code includes information bits and parity bits, the parity bits being processed by a receiving device to recover information bits corrupted by transmission path errors,

wherein the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits,

wherein the information matrix portion is represented by a parity check matrix initial value table, and

wherein the parity check matrix initial value table, having each row indicating positions of elements ‘1’ in corresponding 360 columns of the information matrix portion corresponding to a subset of information bits used in calculating the parity bits in the LDPC encoding, is as follows

3 394 1014 1214 1361 1477 1534 1660 1856 2745 2987 2991 3124 3155

59 136 528 781 803 928 1293 1489 1944 2041 2200 2613 2690 2847

155 245 311 621 1114 1269 1281 1783 1995 2047 2672 2803 2885 3014

79 870 974 1326 1449 1531 2077 2317 2467 2627 2811 3083 3101 3132

4 582 660 902 1048 1482 1697 1744 1928 2628 2699 2728 3045 3104

175 395 429 1027 1061 1068 1154 1168 1175 2147 2359 2376 2613 2682

1388 2241 3118 3148

143 506 2067 3148

1594 2217 2705

398 988 2551

1149 2588 2654

678 2844 3115

1508 1547 1954

1199 1267 1710

2589 3163 3207

1 2583 2974

2766 2897 3166

929 1823 2742

1113 3007 3239

1753 2478 3127

0 509 1811

1672 2646 2984

965 1462 3230

3 1077 2917

1183 1316 1662

968 1593 3239

64 1996 2226

1442 2058 3181

513 973 1058

1263 3185 3229

681 1394 3017

419 2853 3217

3 2404 3175

2417 2792 2854

1879 2940 3235

647 1704 3060, and

transmit the digital television broadcast signal including the LDPC code word.

2. The transmitting device according to claim 1 , wherein

a row of the parity check matrix initial value table is represented by i and a length of the parity bits of the LDPC code word is represented by M, a 2+360×(i−1)-th column of the parity check matrix is obtained by a cyclic shift of a 1+360×(i−1)-th column of the parity check matrix indicating a position of an element 1 in the parity check matrix initial value table downward by q=M/360.

3. The transmitting device according to claim 2 , wherein

for the 1+360×(i−1)-th column of the parity check matrix,

an i-th row of the parity check matrix initial value table represents a row number of the element 1 of the 1+360×(i−1)-th column of the parity check matrix, and

for each column from the 2+360×(i−1)-th column to a 360×i-th column being a column other than the 1+360×(i−1)-th column of the parity check matrix,

an i-th row and j-th column value of the parity check matrix initial value table is represented as h i,j and the row number of a j-th element 1 of a w-th column of a parity check matrix H is represented as H w-j ,

a row number H w-j of the element 1 of the w-th column being a column other than the 1+360×(i−1)-th column of the parity check matrix is represented by equation

H w-j =mod( h i,j +mod(( w− 1), 360)× M/ 360 , M ).

4. The transmitting device according to claim 1 , wherein

the parity check matrix has no cycle- 4 .

5. The transmitting device according to claim 1 , wherein

the parity check matrix of the LDPC code belongs to an ensemble in which a performance threshold being a ratio of signal power to noise power at which a bit error rate starts to decrease is a predetermined value or smaller is found by multi-edge type density evolution.

6. A method for generating a digital television broadcast signal and for decreasing a signal-to-noise power ratio of the generated digital television broadcast signal, the method comprising:

receiving data to be transmitted in a digital television broadcast signal;

performing low density parity check (LDPC) encoding, in an LDPC encoding circuitry, on input bits of the received data according to a parity check matrix of an LDPC code having a code length of 16200 bits and a code rate of 12/15 to generate an LDPC code word, the LDPC code enabling error correction processing to correct errors generated in a transmission path of the digital television broadcast signal;

wherein the LDPC code word includes information bits and parity bits, the parity bits being processed by a receiving device to recover information bits corrupted by transmission path errors,

the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits,

the information matrix portion is represented by a parity check matrix initial value table, and

the parity check matrix initial value table, having each row indicating positions of elements ‘1’ in corresponding 360 columns of the information matrix portion corresponding to a subset of information bits used in calculating the parity bits in the LDPC encoding, is as follows:

3 394 1014 1214 1361 1477 1534 1660 1856 2745 2987 2991 3124 3155

59 136 528 781 803 928 1293 1489 1944 2041 2200 2613 2690 2847

155 245 311 621 1114 1269 1281 1783 1995 2047 2672 2803 2885 3014

79 870 974 1326 1449 1531 2077 2317 2467 2627 2811 3083 3101 3132

4 582 660 902 1048 1482 1697 1744 1928 2628 2699 2728 3045 3104

175 395 429 1027 1061 1068 1154 1168 1175 2147 2359 2376 2613 2682

1388 2241 3118 3148

143 506 2067 3148

1594 2217 2705

398 988 2551

1149 2588 2654

678 2844 3115

1508 1547 1954

1199 1267 1710

2589 3163 3207

1 2583 2974

2766 2897 3166

929 1823 2742

1113 3007 3239

1753 2478 3127

0 509 1811

1672 2646 2984

965 1462 3230

3 1077 2917

1183 1316 1662

968 1593 3239

64 1996 2226

1442 2058 3181

513 973 1058

1263 3185 3229

681 1394 3017

419 2853 3217

3 2404 3175

2417 2792 2854

1879 2940 3235

647 1704 3060; and

transmitting, by a broadcast transmitter, the digital television broadcast signal including the LDPC code word.

7. A receiving device for use in an environment where a signal-to-noise power ratio of a received digital television broadcast signal can be reduced, the receiving device comprising:

a receiver configured to receive a digital television broadcast signal including a low density parity check (LDPC) code word; and

circuitry configured to:

decode the LDPC code word; and

process the decoded LDPC code word for presentation of the digital television broadcast signal, wherein

input bits of data to be transmitted in the digital television broadcast signal are LDPC encoded according to

a parity check matrix initial value table of an LDPC code having a code length of 16200 bits and a code rate of 12/15 to generate the LDPC code word, the LDPC code enabling error correction processing to correct errors generated in a transmission path of the digital television broadcast signal,

the LDDC code word includes information bits and parity bits, the parity bits being processed by the receiving device to recover information bits corrupted by transmission path errors,

wherein the parity check matrix initial value table of the LDPC code according to which the input bits are LDPC encoded is as follows,

3 394 1014 1214 1361 1477 1534 1660 1856 2745 2987 2991 3124 3155

59 136 528 781 803 928 1293 1489 1944 2041 2200 2613 2690 2847

155 245 311 621 1114 1269 1281 1783 1995 2047 2672 2803 2885 3014

79 870 974 1326 1449 1531 2077 2317 2467 2627 2811 3083 3101 3132

4 582 660 902 1048 1482 1697 1744 1928 2628 2699 2728 3045 3104

175 395 429 1027 1061 1068 1154 1168 1175 2147 2359 2376 2613 2682

1388 2241 3118 3148

143 506 2067 3148

1594 2217 2705

398 988 2551

1149 2588 2654

678 2844 3115

1508 1547 1954

1199 1267 1710

2589 3163 3207

1 2583 2974

2766 2897 3166

929 1823 2742

1113 3007 3239

1753 2478 3127

0 509 1811

1672 2646 2984

965 1462 3230

3 1077 2917

1183 1316 1662

968 1593 3239

64 1996 2226

1442 2058 3181

513 973 1058

1263 3185 3229

681 1394 3017

419 2853 3217

3 2404 3175

2417 2792 2854

1879 2940 3235

647 1704 3060.

8. The receiving device according to claim 7 , wherein

the LDPC code word is encoded based on a parity check matrix of the LDPC code,

the parity check matrix includes an information matrix part corresponding to the information bits and a parity matrix part corresponding to the parity bits,

the information matrix part being represented by the parity check matrix initial value table, and

each row of the parity check matrix initial value table indicates positions of elements “1” in corresponding 360 columns of the information matrix part corresponding to a subset of information bits used in calculating the parity bits in the LDPC encoding.

9. The receiving device according to claim 8 , wherein

a row of the parity check matrix initial value table is represented by i and a length of the parity bits of the LDPC code word is represented by M, a 2+360×(i−1)-th column of the parity check matrix is obtained by a cyclic shift of a 1+360×(i−1)-th column of the parity check matrix indicating a position of an element 1 in the parity check matrix initial value table downward by q=M360.

10. The receiving device according to claim 9 , wherein

for the 1+360×(i−1)-th column of the parity check matrix,

an i-th row of the parity check matrix initial value table represents a row number of the element 1 of the 1+360×(i−1)-th column of the parity check matrix, and

for each column from the 2+360×(i−1)-th column to a 360×i-th column being a column other than the 1+360×(i−1)-th column of the parity check matrix,

an i-th row and j-th column value of the parity check matrix value table is represented as h i,j and a row number of a j-th element 1 of a w-th column of a parity check matrix H is represented as H w-j ,

a row number H w-j of the element 1 of the w-th column being a column other than the 1+360×(i−1)-th column of the parity check matrix is represented by equation

H w-j =mod( h i,j +mod(( w− 1), 360)× M/ 360 , M ).

11. The receiving device according to claim 7 , wherein the circuitry is further configured to:

interleave only parity bits of the LDPC code word.

12. The receiving device according to claim 7 , wherein

the parity check matrix has no cycle- 4 .

13. The receiving device according to claim 7 , wherein

the parity check matrix of the LDPC code belongs to an ensemble in which a performance threshold being a ratio of signal power to noise power at which a bit error rate starts to decrease is a predetermined value or smaller is found by multi-edge type density evolution.

14. A method for use by a receiving device in an environment where a signal-to-noise power ratio of a digital television broadcast signal can be reduced, the method comprising:

receiving a digital television broadcast signal including an LDPC (low density parity check) code word;

decoding, by decoding circuitry, the LDPC code word; and

processing the decoded LDPC code word for presentation of the digital television broadcast signal, wherein

input bits of data to be transmitted in the digital television broadcast signal are LDPC encoded according to a parity check matrix initial value table of an LDPC code having a code length N of 16200 bits and a code rate r of 12/15 to generate the LDPC code word, the LDPC code enabling error correction processing to correct errors generated in a transmission path of the digital television broadcast signal,

the LDPC code word includes information bits and parity bits, the parity bits being processed by the receiving device to recover information bits corrupted by transmission path errors,

the parity check matrix initial value table of the LDPC code according to which the input bits are LDPC encoded is as follows,

3 394 1014 1214 1361 1477 1534 1660 1856 2745 2987 2991 3124 3155

59 136 528 781 803 928 1293 1489 1944 2041 2200 2613 2690 2847

155 245 311 621 1114 1269 1281 1783 1995 2047 2672 2803 2885 3014

79 870 974 1326 1449 1531 2077 2317 2467 2627 2811 3083 3101 3132

4 582 660 902 1048 1482 1697 1744 1928 2628 2699 2728 3045 3104

175 395 429 1027 1061 1068 1154 1168 1175 2147 2359 2376 2613 2682

1388 2241 3118 3148

143 506 2067 3148

1594 2217 2705

398 988 2551

1149 2588 2654

678 2844 3115

1508 1547 1954

1199 1267 1710

2589 3163 3207

1 2583 2974

2766 2897 3166

929 1823 2742

1113 3007 3239

1753 2478 3127

0 509 1811

1672 2646 2984

965 1462 3230

3 1077 2917

1183 1316 1662

968 1593 3239

64 1996 2226

1442 2058 3181

513 973 1058

1263 3185 3229

681 1394 3017

419 2853 3217

3 2404 3175

2417 2792 2854

1879 2940 3235

647 1704 3060.

15. The method according to claim 14 , wherein

the LDPC code word is encoded based on a parity check matrix of the LDPC code,

the parity check matrix includes an information matrix part corresponding to the information bits and a parity matrix part corresponding to the parity bits,

the information matrix part being represented by the parity check matrix initial value table, and

each roe of the parity check matrix initial value table indicates positions of elements “1 ” in corresponding 360 columns of the information matrix part corresponding to a subset of information bits used in calculating the parity bits in the LDPC encoding.

16. The method according to claim 15 , wherein

a row of the parity check matrix initial value table is represented by i and a length of the parity bits of the LDPC code word is represented by M, a 2+360×(i−1)-th column of the parity check matrix is obtained by a cyclic shift of a 1+360×(i−1)-th column of the parity check matrix indicating a position of an element 1 in the parity check matrix initial value table downward by q=M/360.

17. The method according to claim 16 , wherein

for the 1+360×(i−1)-th column of the parity check matrix,

an i-th row of the parity check matrix initial value table represents a row number of the element 1 of the 1+360×(i−1)-th column of the parity check matrix, and

for each column from the 2+360×(i−1)-th column to a 360×i-th column being a column other than the 1+360×(i−1)-th column of the parity check matrix,

an i-th row and j-th column value of the parity check matrix initial value table is represented as h i,j and a row number of a j-th element 1 of a w-th column of a parity check matrix H is represented as H w-j ,

a row number H w-j of the element 1 of the w-th column being a column other than the 1+360×(i−1)-th column of the parity check matrix is represented by equation

H w-j =mod( h i,j +mod(( w− 1), 360)× M/ 360 , M ).

18. The method according to claim 14 , wherein

the parity check matrix has no cycle- 4 .

19. The method according to claim 14 , wherein

the parity check matrix of the LDPC code belongs to an ensemble in which a performance threshold being signal power/noise power at which a bit error rate starts to decrease is a predetermined value or smaller is found by multi-edge type density evolution.