IP Library Granted Patent US 10,433,421
Granted Patent B2
US 10,433,421 · App. 13/727,439 · Granted Oct 1, 2019

Reduced capacitance land pad

Inventors: Zhichao Zhang (Chandler, AZ); Tao Wu (Chandler, AZ); Gaurav Chawla (Chandler, AZ); Jeffrey Lee (Chandler, AZ)
Assignee: Intel Corporation
H05K1/113H05K1/025H05K1/0243H05K3/3452H05K2201/0969H05K2201/09663H05K2201/09881H05K2201/10719Y10T29/49165
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Quick Facts
Patent No.
US 10,433,421
App. No.
13/727,439
Granted
Oct 1, 2019
Kind
B2
Abstract

A land grid array (LGA) land pad having reduced capacitance is disclosed. The conductive portion of a land pad that overlaps a parallel ground plane within the substrate is reduced by one or more non-conductive voids though the thickness of the conductive portion of the land pad. The voids may allow the contact area of the land pad, as defined by the perimeter of the land pad, to remain the same while reducing the conductive portion that overlaps the parallel ground plane. Capacitance between the land pad and the parallel ground plane is reduced by an amount proportional to the reduction in overlapping conductive area.

Claims (15)

1. A structure, comprising:

a substrate having one or more dielectric layers including a conductive trace and a ground plane; and

a plurality of land pads on the surface of the substrate, the land pads each comprising:

a conductive portion electrically coupled with the conductive trace by one or more vias, the conductive portion having a contact area and a thickness, the contact area for making electrical contact to an individual land grid array (LGA) contact, wherein the contact area is parallel to the ground plane; and

one or more non-conductive voids in the contact area and extending through the thickness of the conductive portion, wherein the conductive portion is continuous around the one or more non-conductive voids.

2. The structure of claim 1 , wherein the contact area is defined by a contact perimeter.

3. The structure of claim 1 , wherein the one or more voids include an non-conductive material.

4. The structure of claim 1 , wherein the one or more voids have a circular cross-section.

5. The structure of claim 1 , wherein the one or more voids have a polygonal cross-section.

6. The structure of claim 1 , wherein the conductive portion comprises copper.

7. The structure of claim 1 , further comprising a land grid array socket including a respective plurality of land grid array contacts in electrical contact with the plurality of land pads, wherein the one or more voids are sized and positioned to ensure electrical coupling of the land grid array contact with the land pad.

8. The structure of claim 7 , wherein the one or more voids have a width less than a tip width of the land grid array contact.

9. The structure of claim 8 , wherein the width is from 10 μm to 350 μm.

10. The structure of claim 1 , wherein the one or more voids occupy from 1% to 60% of the contact area.

11. The structure of claim 1 , wherein the one or more voids occupy 20-30% of the contact area.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 21, 2013
From: ZHANG, ZHICHAO; WU, TAO; CHAWLA, GAURAV; LEE, JEFFREY
To: INTEL CORPORATION
Reel/Frame 029852/0566 →
Continuity (1)
Related Publication 20140174808A1 · Jun 26, 2014
Cited By (1)
US 12,672,565