Broadcast scan network

1. A distributed test circuit, comprising:

a plurality of circuit partitions arranged in series to form a scan path;

each of the circuit partitions comprising a scan multiplexer, a test data register, and a segment insertion bit circuit;

the scan multiplexer of each of the circuit partitions providing inputs to a corresponding test data register of each of the circuit partitions;

control logic to generate a broadcast mode select signal to the scan multiplexer of each of the circuit partitions to place the test circuit in a broadcast mode when the broadcast mode select signal is asserted, and to switch the test circuit to a daisy mode when the broadcast mode select signal is de-asserted; and

each segment insertion bit circuit operable to include or bypass the corresponding circuit partition from the scan path.

2. The distributed test circuit of claim 1 , further comprising:

the test circuit configured in the broadcast mode to apply test data for each of the circuit partitions simultaneously to each corresponding test data register; and

the test circuit configured in the daisy mode to shift the test data sequentially along the series arrangement of circuit partitions.

3. The distributed test circuit of claim 1 , each segment insertion bit circuit comprising:

a shift cell coupled to receive test data from the test data register;

an update cell coupled to receive the test data from the shift cell;

an update pipeline coupled to provide a shift signal to the shift cell; and

a control circuit coupled to freeze operation of the shift cell during the broadcast mode.

4. The distributed test circuit of claim 3 , the control circuit comprising a gate receiving the broadcast mode select signal and an output of the update pipeline, the gate coupled to select a test data input to the update cell.

5. The distributed test circuit of claim 3 , each segment insertion bit circuit having operational states given by the following table:

Update

Broadcast Mode

Test Data

Test Circuit

SIB State

Cell

Select Signal

Register

Mode

Open and

1

0

Active

Daisy

unfrozen

Closed and

0

0

Bypass

Daisy

unfrozen

Bypass

Open and Frozen

1

1

Active

Broadcast

Closed and

0

1

Bypass

Broadcast

Frozen

Bypass.

6. A distributed test circuit, comprising:

a plurality of circuit clusters arranged in series to form a scan path;

each of the circuit clusters comprising a scan multiplexer, and a segment insertion bit circuit, and a series arrangement of circuit partitions;

each circuit partition of each of the circuit clusters comprising a test data register;

the scan multiplexer of each of the circuit clusters providing inputs to a first circuit partition of the series arrangement of circuit partitions in the corresponding circuit cluster;

control logic to place the test circuit in a broadcast mode when a broadcast select signal is asserted, and to switch the test circuit to a daisy mode when the broadcast select signal is de-asserted; and

each segment insertion bit circuit operable to include or bypass the corresponding circuit cluster from the scan path.

7. The distributed test circuit of claim 6 , further comprising:

the test circuit configured in the broadcast mode to apply test data for each of the circuit partitions simultaneously to each corresponding test data register; and

the test circuit configured in the daisy mode to shift the test data sequentially along the series arrangement of circuit partitions.

8. The distributed test circuit of claim 6 , wherein each circuit partition comprises:

a partition-level scan multiplexer, the test data register, and a partition-level segment insertion bit circuit, the partition-level scan multiplexer providing inputs to the test data register.

9. The distributed test circuit of claim 8 , wherein each of the series arrangement of circuit partitions of each of the circuit clusters further comprises:

partition-level control logic to generate a partition-level broadcast select signal to the partition-level scan multiplexer of each of the circuit partitions in the series arrangement of circuit partitions, to place each circuit partition of the series arrangement of circuit partitions in the broadcast mode when the partition-level broadcast select signal is asserted, and to switch each circuit partition of the series arrangement of circuit partitions to the daisy mode when the partition-level broadcast select signal is de-asserted; and

the partition-level segment insertion bit circuit operable to include or bypass the corresponding circuit partition of the series arrangement of circuit partitions from the scan path.

10. The distributed test circuit of claim 8 , each partition-level segment insertion bit circuit comprising:

a shift cell coupled to receive test data from the test data register;

an update cell coupled to receive the test data from the shift cell;

an update pipeline coupled to provide a shift signal to the shift cell; and

a control circuit coupled to freeze operation of the shift cell during the broadcast mode.

11. The distributed test circuit of claim 10 , the control circuit comprising a gate receiving the broadcast mode select signal and an output of the update pipeline, the gate coupled to select a test data input to the update cell.

12. The distributed test circuit of claim 10 , each partition-level segment insertion bit circuit having operational states given by the following table:

Update

Broadcast Mode

Test Data

Test Circuit

SIB State

Cell

Select Signal

Register

Mode

Open and

1

0

Active

Daisy

unfrozen

Closed and

0

0

Bypass

Daisy

unfrozen

Bypass

Open and Frozen

1

1

Active

Broadcast

Closed and

0

1

Bypass

Broadcast

Frozen

Bypass.