Reconfigurable camera serial interface
Some embodiments include apparatuses and methods using the apparatuses. Some of the apparatuses include a circuit structure that can be configured to operate in either the C-PHY mode or the D-PHY mode of the MIPI specification. In one device, the circuit structure can be included in a receiver of the device and configured to operate in the C-PHY mode. In another device, the circuit structure can be included in a receiver of the device and configured to operate in the D-PHY mode.
1. An apparatus comprising:
nodes to receive signals based on C-PHY mode of Mobile Industry Processor Interface (MIPI) specification;
a first comparator including input nodes coupled to two of the nodes;
a second comparator including input nodes coupled to two of the nodes;
a third comparator including input nodes coupled to two of the nodes;
a first delay locked-loop coupled to an output node of the first comparator, the first delay locked-loop including first and second digital controlled delay lines coupled in series with each other;
a second delay locked-loop coupled to an output node of the second comparator, the second delay locked-loop including first and second digital controlled delay lines coupled in series with each other;
a third delay locked-loop coupled to an output node of the third comparator, the third delay locked-loop including first and second digital controlled delay lines coupled in series with each other; and
circuitry to provide a code to adjust a time delay of at least one of the first second, and third delay locked-loops.
2. The apparatus of claim 1 , further comprising:
a first data recover circuit coupled to the first delay locked-loop;
a second data recover circuit coupled to the second delay locked-loop;
a third data recover circuit coupled to the third delay locked-loop; and
a clock recovery circuit coupled to the first, second, and third data recover circuits.
3. An apparatus comprising:
nodes to receive signals based on C-PHY mode of Mobile Industry Processor Interface (MIPI) specification;
a first comparator including input nodes coupled to two of the nodes;
a second comparator including input nodes coupled to two of the nodes;
a third comparator including input nodes coupled to two of the nodes;
a first delay locked-loop coupled to an output node of the first comparator, the first delay locked-loop including first and second digital controlled delay lines coupled in series with each other;
a second delay locked-loop coupled to an output node of the second comparator, the second delay locked-loop including first and second digital controlled delay lines coupled in series with each other;
a third delay locked-loop coupled to an output node of the third comparator, the third delay locked-loop including first and second digital controlled delay lines coupled in series with each other;
a first data recover circuit coupled to the first delay locked-loop;
a second data recover circuit coupled to the second delay locked-loop;
a third data recover circuit coupled to the third delay locked-loop; and
a clock recovery circuit coupled to the first, second, and third data recover circuits, wherein:
the first and second digital controlled delay lines of the first delay locked-loop include a same number of delay stages;
the first and second digital controlled delay lines of the second delay locked-loop include a same number of delay stages; and
the first and second digital controlled delay lines of the third delay locked-loop include a same number of delay stages.
4. An apparatus comprising:
nodes to receive signals based on C-PHY mode of Mobile Industry Processor Interface (MIPI) specification;
a first comparator including input nodes coupled to two of the nodes;
a second comparator including input nodes coupled to two of the nodes;
a third comparator including input nodes coupled to two of the nodes;
a first delay locked-loop coupled to an output node of the first comparator, the first delay locked-loop including first and second digital controlled delay lines coupled in series with each other;
a second delay locked-loop coupled to an output node of the second comparator, the second delay locked-loop including first and second digital controlled delay lines coupled in series with each other;
a third delay locked-loop coupled to an output node of the third comparator, the third delay locked-loop including first and second digital controlled delay lines coupled in series with each other;
a first data recover circuit coupled to the first delay locked-loop;
a second data recover circuit coupled to the second delay locked-loop;
a third data recover circuit coupled to the third delay locked-loop; and
a clock recovery circuit coupled to the first, second, and third data recover circuits, wherein:
the first data recover circuit includes a multiplexor coupled to output nodes of the first delay locked-loop;
the second data recover circuit includes a multiplexor coupled to output nodes of the second delay locked-loop; and
the third data recover circuit includes a multiplexor coupled to output nodes of the third delay locked-loop.
5. The apparatus of claim 4 , wherein the first data recovery circuit includes a data sampler coupled to an output node of the first multiplexor.
6. An apparatus comprising:
nodes to receive signals based on C-PHY mode of Mobile Industry Processor Interface (MIPI) specification;
a first comparator including input nodes coupled to two of the nodes;
a second comparator including input nodes coupled to two of the nodes;
a third comparator including input nodes coupled to two of the nodes;
a first delay locked-loop coupled to an output node of the first comparator, the first delay locked-loop including first and second digital controlled delay lines coupled in series with each other;
a second delay locked-loop coupled to an output node of the second comparator, the second delay locked-loop including first and second digital controlled delay lines coupled in series with each other;
a third delay locked-loop coupled to an output node of the third comparator, the third delay locked-loop including first and second digital controlled delay lines coupled in series with each other;
a first data recover circuit coupled to the first delay locked-loop;
a second data recover circuit coupled to the second delay locked-loop;
a third data recover circuit coupled to the third delay locked-loop; and
a clock recovery circuit coupled to the first, second, and third data recover circuits, wherein the clock recovery circuit includes a finite state machine to provide a code to control the first, second, and third delay locked-loops.
7. The apparatus of claim 6 , wherein a value of the code is based on a comparison between a target duty cycle and a duty cycle of a clock signal generated by the clock recovery circuit.
8. An apparatus comprising:
nodes to receive signals based on C-PHY mode of Mobile Industry Processor Interface (MIPI) specification;
a first comparator including input nodes coupled to two of the nodes;
a second comparator including input nodes coupled to two of the nodes;
a third comparator including input nodes coupled to two of the nodes;
a first delay locked-loop coupled to an output node of the first comparator, the first delay locked-loop including first and second digital controlled delay lines coupled in series with each other;
a second delay locked-loop coupled to an output node of the second comparator, the second delay locked-loop including first and second digital controlled delay lines coupled in series with each other;
a third delay locked-loop coupled to an output node of the third comparator, the third delay locked-loop including first and second digital controlled delay lines coupled in series with each other;
a fourth comparator including input nodes coupled to two of the nodes;
a fifth comparator including input nodes coupled to two of the nodes;
a sixth comparator including input nodes coupled to two of the nodes;
a fourth delay locked-loop coupled to an output node of the fourth comparator, the fourth delay locked-loop including first and second digital controlled delay lines coupled in series with each other;
a fifth delay locked-loop coupled to an output node of the fifth comparator, the fifth delay locked-loop including first and second digital controlled delay lines coupled in series with each other; and
a sixth delay locked-loop coupled to an output node of the sixth comparator, the sixth delay locked-loop including first and second digital controlled delay lines coupled in series with each other.
9. The apparatus of claim 8 , further comprising:
a fourth data recover circuit coupled to the fourth delay locked-loop;
a fifth data recover circuit coupled to the fifth delay locked-loop;
a sixth data recover circuit coupled to the sixth delay locked-loop; and
an additional clock recovery circuit coupled to the fourth, fifth, and sixth data recover circuits.
10. An apparatus comprising:
nodes to receive signals based on C-PHY mode of Mobile Industry Processor Interface (MIPI) specification;
a first comparator including input nodes coupled to two of the nodes;
a second comparator including input nodes coupled to two of the nodes;
a third comparator including input nodes coupled to two of the nodes;
a first delay circuit coupled to an output node of the first comparator;
a second delay circuit coupled to an output node of the second comparator;
a third delay circuit coupled to an output node of the third comparator; and
a clock recovery circuit to generate a clock signal, the clock signal including:
a first edge based on an edge of a first signal generated based on an earliest data transition among data transitions of signals received that the nodes;
a second edge based on an edge of a second signal, the second signal being a delayed version of the first signal; and
a finite state machine to provide a code to adjust a time delay of each of the first and second delay circuits.
11. The apparatus of claim 10 , wherein each of the first and second delay circuits include a digital controlled delay line.
12. The apparatus of claim 10 , wherein the first edge of the clock signal is a rising edge and the second edge of the clock signal is a falling edge.
13. The apparatus of claim 12 , wherein the edge of the first signal is a rising edge, and the edge of the second signal is a rising edge.
14. An apparatus comprising:
nodes to receive signals based on D-PHY mode of Mobile Industry Processor Interface (MIPI) specification;
a first comparator including input nodes coupled to two of the nodes;
a second comparator including input nodes coupled to two of the nodes;
a third comparator including input nodes coupled to two of the nodes;
a first delay locked-loop coupled to an output node of the first comparator;
a second delay locked-loop coupled to an output node of the second comparator;
a third delay locked-loop coupled to an output node of the third comparator;
fifth, fourth, and sixth comparators coupled to fifth, fourth, and sixth delay locked-loop, respectively; and
a clock recovery circuit coupled to the first, second, third, fourth, fifth, and sixth delay locked-loops, wherein the fourth, fifth, and sixth comparators and the fourth, fifth, and sixth delay locked-loop are disabled during operations of the first, second, and third comparators and first, second, and third delay locked-loops.
15. The apparatus of claim 14 , wherein:
the first delay locked-loop including first and second digital controlled delay lines coupled in series with each other;
the second delay locked-loop including first and second digital controlled delay lines coupled in series with each other; and
the third delay locked-loop including first and second digital controlled delay lines coupled in series with each other.
16. The apparatus of claim 14 , wherein the clock recovery circuit includes a finite state machine to provide a code to control the first and second delay locked-loops.
17. The apparatus of claim 14 , further comprising:
a multiplexor coupled output nodes of the first delay locked-loop; and
a data sampler coupled to an output node of the multiplexor.
18. An apparatus comprising:
a receiver to receive signals based on Mobile Industry Processor Interface (MIPI) specification;
a processor to process data information included in the signals; and
antenna coupled to the processor, the receiver including:
a first comparator including input nodes coupled to two of the nodes;
a second comparator including input nodes coupled to two of the nodes;
a third comparator including input nodes coupled to two of the nodes;
a first delay locked-loop coupled to an output node of the first comparator, the first delay locked-loop including first and second digital controlled delay lines coupled in series with each other;
a second delay locked-loop coupled to an output node of the second comparator, the second delay locked-loop including first and second digital controlled delay lines coupled in series with each other;
a third delay locked-loop coupled to an output node of the third comparator, the second delay locked-loop including first and second digital controlled delay lines coupled in series with each other; and
circuitry to provide a code to adjust a time delay of at least one of the first second, and third delay locked-loops.
19. An apparatus comprising:
a receiver to receive signals based on Mobile Industry Processor Interface (MIPI) specification;
a processor to process data information included in the signals; and
antenna coupled to the processor, the receiver including:
a first comparator including input nodes coupled to two of the nodes;
a second comparator including input nodes coupled to two of the nodes;
a third comparator including input nodes coupled to two of the nodes;
a first delay locked-loop coupled to an output node of the first comparator, the first delay locked-loop including first and second digital controlled delay lines coupled in series with each other;
a second delay locked-loop coupled to an output node of the second comparator, the second delay locked-loop including first and second digital controlled delay lines coupled in series with each other;
a third delay locked-loop coupled to an output node of the third comparator, the second delay locked-loop including first and second digital controlled delay lines coupled in series with each other;
a fourth comparator including input nodes coupled to two of the nodes;
a fifth comparator including input nodes coupled to two of the nodes;
a sixth comparator including input nodes coupled to two of the nodes;
a fourth delay locked-loop coupled to an output node of the fourth comparator, the fourth delay locked-loop including first and second digital controlled delay lines coupled in series with each other;
a fifth delay locked-loop coupled to an output node of the fifth comparator, the fifth delay locked-loop including first and second digital controlled delay lines coupled in series with each other; and
a sixth delay locked-loop coupled to an output node of the sixth comparator, the sixth delay locked-loop including first and second digital controlled delay lines coupled in series with each other.