Anneal after trench sidewall implant to reduce defects
An electronic device includes a semiconductor substrate having a plurality of trenches formed therein. Each trench includes a sidewall having a doped region, a sidewall liner, and a filler material. The substrate has a slip density of less than 5 cm −2 . The low slip density is achieved by a novel annealing protocol performed after implanting the dopant in the sidewall to repair damage and/or stress caused by the implant process.
1. An electronic device, comprising:
a substrate including a semiconductor surface;
a plurality of trenches within the substrate, each trench including:
a sidewall having a doped region;
a sidewall liner; and
a filler material,
wherein the substrate has a slip density of fewer than 5 cm −2 .
2. The device of claim 1 , wherein the sidewall liner comprises silicon dioxide.
3. The device of claim 1 , wherein the doped region extends along the sidewall to a depth less than a full depth of the trench.
4. The device of claim 1 , wherein the filler material comprises amorphous silicon.
5. The device of claim 4 , wherein the filler material provides a conductive path between a metal via and the substrate.
6. The device of claim 1 , wherein the filler material contacts a doped region at a bottom of the trench.
7. The device of claim 1 , wherein the trench passes through a doped buried layer in the substrate.
8. The device of claim 7 , wherein the doped sidewall extends to a depth as least as deep as an upper boundary of the buried layer.
9. The device of claim 1 , wherein the trench has a depth within a range between about 5 μm and about 35 μm.
10. The device of claim 1 , wherein the trench is located between first and second transistors, thereby isolating the first transistor from the second transistor.
11. An integrated circuit (IC), comprising:
a substrate including a semiconductor surface;
a filled trench with sidewalls lined with a liner oxide layer having locally doped substrate edges of the trenches which extend in a depth direction along the sidewalls of the trenches from a top of the semiconductor surface to a first depth; and
a first transistor and a second transistor dielectrically isolated from one another by the filled trench,
wherein the IC has a slip density of fewer than 5 cm −2 .
12. The IC of claim 11 , wherein the locally doped substrate edges of the trenches have a minimum dopant concentration of 5×10 17 cm −3 .
13. The IC of claim 11 , wherein the substrate comprises bulk silicon or an epitaxial silicon layer on bulk silicon.
14. The IC of claim 11 , wherein the filled trenches comprise top side contact (TSC) trenches which include doped polysilicon over the liner oxide layer, and have a bottom of the trenches without the liner oxide layer and with a bottom doped region so that the doped polysilicon provides an ohmic contact to the substrate.
15. The IC of claim 14 , wherein the semiconductor surface includes a buried layer, and wherein a doping in the doped substrate edges has a depth that extends into the buried layer.
16. The IC of claim 11 , wherein the filled trenches are 5 μm to 35 μm deep.
17. The IC of claim 11 , wherein the IC has a slip density of <1 cm −2 .
18. The IC of claim 11 , wherein the IC includes at least one laterally diffused metal-oxide-semiconductor (LDMOS) transistor.