Dual channel FinFETs having uniform fin heights
A method of making a semiconductor device including forming a first blanket layer on a substrate; forming a second blanket layer on the first blanket layer; patterning a first fin of a first transistor region and a second fin of a second transistor region in the first blanket layer and the second blanket layer; depositing a mask on the second transistor region; removing the first fin to form a trench; growing a first semiconductor layer in the trench where the first fin was removed; and growing a second semiconductor layer on the first semiconductor layer.
1. A semiconductor device comprising:
a n-type field effect transistor (NFET) comprising a plurality of first fins extending from a substrate, each of the plurality of first fins comprising an p-doped silicon portion extending from the substrate and a portion consisting of silicon extending directly from the p-doped silicon portion, the p-doped silicon portion of each of the plurality of first fins having a rounded bottom edge, and the p-doped silicon portion being a single discrete layer of silicon doped with a p-type dopant; and
a p-type field effect transistor (PFET) comprising a plurality of second fins extending from the substrate, each of the plurality of second fins comprising an n-doped silicon portion extending from the substrate and a portion consisting of silicon germanium extending directly from the n-doped silicon portion, the n-doped silicon portion of each of the plurality of second fins having a substantially flat bottom edge, and the n-doped silicon portion being a single discrete layer of silicon doped with an n-type dopant.
2. The semiconductor device of claim 1 , wherein the n-doped silicon portion of the plurality of second fins has a thickness of about 20 to about 60 nanometers.
3. The semiconductor device of claim 1 , wherein the portion consisting of silicon germanium of each of the plurality of second fins has a thickness of about 20 to about 60 nanometers.
4. The semiconductor device of claim 1 , wherein the p-type dopant is boron.
5. The semiconductor device of claim 1 , wherein the p-type dopant is gallium.
6. The semiconductor device of claim 1 , wherein the p-type dopant is indium.
7. The semiconductor device of claim 1 , wherein the substrate comprises silicon.