Method and device of preventing merging of resist-protection-oxide (RPO) between adjacent structures
A semiconductor device having a first region and a second region is provided. The first region has a first protruding structure and a second protruding structure. The second region has a third protruding structure and a fourth protruding structure. First, second, third, and fourth epi-layers are formed on the first, second, third, and fourth protruding structures, respectively. The first and second epi-layers are covered with a first photoresist layer while leaving the third and fourth epi-layers exposed. A dielectric layer is formed over the first photoresist layer and over the third and fourth epi-layers. A portion of the dielectric layer is covered with a second photoresist layer. The portion of the dielectric layer is formed over the third and fourth epi-layers. Portions of the dielectric layer not protected by the first and second photoresist layers are etched. The first and second photoresist layers are removed.
1. A semiconductor device, comprising:
a first protruding structure and a second protruding structure each protruding out of an isolation structure, the first and second protruding structures being disposed in a first region of the semiconductor device;
a first epi-layer and a second epi-layer formed on the first and second protruding structures, respectively, wherein the first and second epi-layers each have a silicided surface;
a third protruding structure and a fourth protruding structure each protruding out of the isolation structure, the third and fourth protruding structures being disposed in a second region of the semiconductor device;
a third epi-layer and a fourth epi-layer formed on the third and fourth protruding structures, respectively, wherein the third and fourth epi-layers are free of having a silicided surface; and
a recess formed in the isolation structure, the recess circumferentially surrounding the third and fourth epi-layers in 360 degrees in a top view.
2. The semiconductor device of claim 1 , further comprising a dielectric layer disposed on and surrounding the third and fourth epi-layers, wherein the recess circumferentially surrounds the dielectric layer in the top view.
3. The semiconductor device of claim 2 , wherein the dielectric layer is free of being disposed in the first region.
4. The semiconductor device of claim 2 , wherein a portion of the dielectric layer protrudes laterally toward the first region, and wherein a portion of the recess laterally extends beneath the portion of the dielectric layer in the second region.
5. The semiconductor device of claim 2 , wherein a thickness of the dielectric layer is greater than about ½ of a gap separating the first and second epi-layers.
6. The semiconductor device of claim 1 , wherein:
a first portion of the isolation structure disposed between the first and second protruding structures has a first height;
a second portion of the isolation structure not disposed between the first and second protruding structures has a second height; and
the first height is similar to the second height.
7. The semiconductor device of claim 6 , wherein the first height and the second height are within 5 nanometers of one another.
8. The semiconductor device of claim 1 , wherein the recess exhibits a two-step cross-sectional profile.
9. The semiconductor device of claim 1 , wherein the first and second protruding structures are free of having silicided surfaces.
10. The semiconductor device of claim 1 , wherein the first, second, third, and fourth protruding structures are fins from a FinFET device.
11. A semiconductor device, comprising:
a first fin and a second fin each protruding out of a shallow trench isolation (STI), the first and second fins being located in a first region of a FinFET;
a first epi-layer and a second epi-layer formed on the first and second fins, respectively, wherein the first and second epi-layers each have a silicided surface;
a third fin and a fourth fin each protruding out of the STI, the third and fourth fins being located in a second region of the FinFET;
a third epi-layer and a fourth epi-layer formed on the third and fourth fins, respectively, wherein the third and fourth epi-layers are free of having a silicided surface;
a resist-protection oxide (RPO) layer formed on upper surfaces and side surfaces of the third and fourth epi-layers but not on the first and second epi-layers; and
a trench formed in the STI, the trench encircling the RPO layer in multiple directions in a top view.
12. The semiconductor device of claim 11 , wherein the trench exhibits a two-step cross-sectional profile.
13. The semiconductor device of claim 11 , wherein the first and second fins are free of having silicided surfaces.
14. The semiconductor device of claim 11 , wherein:
a first portion of the STI dislocated between the first and second fins has a first height;
a second portion of the STI not located between the first and second fins has a second height; and
the first height exceeds the second height by less than 5 nanometers.
15. A semiconductor device, comprising:
a first protruding structure and a second protruding structure each protruding out of an isolation structure, the first and second protruding structures being disposed in a first region of the semiconductor device, wherein the first and second protruding structures are do not have silicided surfaces;
a first epi-layer and a second epi-layer formed on the first and second protruding structures, respectively, wherein the first and second epi-layers each have a silicided surface;
a third protruding structure and a fourth protruding structure each protruding out of the isolation structure, the third and fourth protruding structures being disposed in a second region of the semiconductor device;
a third epi-layer and a fourth epi-layer formed on the third and fourth protruding structures, respectively, wherein the third and fourth epi-layers are free of having a silicided surface;
a recess formed in the isolation structure, the recess circumferentially surrounding the third and fourth epi-layers in a top view; and
a dielectric layer disposed on and surrounding the third and fourth epi-layers, wherein the third epi-layer and the fourth epi-layer are separated by a portion of the dielectric layer, wherein no portion of the dielectric layer is disposed in the first region, and wherein the recess borders the dielectric layer in at least a first direction and a second direction in the top view, the first direction being different from the second direction.
16. The semiconductor device of claim 15 , wherein the dielectric layer has a lateral protrusion, and wherein a portion of the recess laterally extends beneath the lateral protrusion of the dielectric layer.
17. The semiconductor device of claim 15 , wherein the dielectric layer is thicker than about ½ of a gap separating the first and second epi-layers.
18. The semiconductor device of claim 15 , wherein:
a first portion of the isolation structure disposed between the first and second protruding structures has a first height;
a second portion of the isolation structure not disposed between the first and second protruding structures has a second height; and
the first height is similar to the second height.
19. The semiconductor device of claim 15 , wherein the recess exhibits a two-step cross-sectional profile.
20. The semiconductor device of claim 15 , wherein the first, second, third, and fourth protruding structures are fins from a FinFET device.