IP Library Granted Patent US 10,438,963
Granted Patent B2
US 10,438,963 · App. 15/620,895 · Granted Oct 8, 2019

Method for manufacturing semiconductor device

Inventor: Jaeseong Kim (Chungcheongbuk-do, KR)
Assignee: SK hynix Inc.
H01L27/11582H01L27/11565
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Quick Facts
Patent No.
US 10,438,963
App. No.
15/620,895
Granted
Oct 8, 2019
Kind
B2
Abstract

Provided herein is a method of manufacturing a semiconductor device. The method for manufacturing the semiconductor device includes: alternately stacked first material layers and second material layers on a lower structure; forming first holes passing through the first material layers and the second material layers, each of the first holes defining a channel region; removing the second material layers through the first holes such that interlayer spaces between the first material layers are formed; and forming, through the first holes, conductive patterns which fill respective interlayer spaces.

Claims (74)

1. A method for manufacturing a semiconductor device, comprising:

alternately stacking first material layers and second material layers on a lower structure;

forming first holes passing through the first material layers and the second material layers, each of the first holes defining a channel region;

removing the second material layers through the first holes such that interlayer spaces between the first material layers are formed;

forming, through the first holes, conductive patterns which fill respective interlayer spaces; and

before the forming of the first holes, simultaneously forming a block separation layer dividing the first material layers and the second material layers into block stacks, and line separation layers dividing each of the block stacks into line stacks,

wherein the forming of the first holes comprises forming second holes passing through ends of the respective line stacks,

wherein the removing of the second material layers comprises removing the second material layers disposed on the ends of the respective line stacks through the second holes, and

wherein the forming of the conductive patterns comprises filling the interlayer spaces that are open on the ends of the respective line stacks with the conductive patterns through the second holes.

2. The method according to claim 1 , further comprising:

forming tunnel insulating layers along sidewalls of the first holes and the second holes; and

forming channel layers on the tunnel insulating layers.

3. The method according to claim 2 ,

wherein the lower structure comprises a pipe gate in which a sacrificial layer is embedded, and

wherein the first holes are formed to expose the sacrificial layer,

further comprising:

removing the sacrificial layer before the tunnel insulating layers and the channel layers are formed; and

opening a pipe hole in the pipe gate such that the tunnel insulating layers and the channel layers are allowed to extend into the pipe gate.

4. The method according to claim 3 , wherein the sacrificial layer is made of the same material as material of the second material layers.

5. The method according to claim 3 , wherein the sacrificial layer is formed of a non-metal nitride layer.

6. The method according to claim 2 ,

wherein the lower structure comprises a source region,

wherein the first holes are formed to expose the source region, and

wherein the channel layers are formed to contact the source region.

7. The method according to claim 2 , wherein partial regions of the interlayer spaces are filled with the conductive patterns such that a ring-shaped space is defined in each of the interlayer spaces between the tunnel insulating layers and the conductive patterns.

8. The method according to claim 7 , wherein the ring-shaped space is defined by recessing the conductive patterns before the tunnel insulating layers are formed.

9. The method according to claim 7 , further comprising, before the forming of the tunnel insulating layers:

forming a blocking insulating layer in the ring-shaped space; and

forming a data storage layer on the blocking insulating layer.

10. The method according to claim 9 , further comprising, before the forming of the data storage layer, recessing the blocking insulating layer such that the blocking insulating layer remains to cover a sidewall of each of the conductive patterns and a portion of the ring-shaped space is open.

11. The method according to claim 10 , wherein the data storage layer is disposed in the ring-shaped space.

12. The method according to claim 2 ,

wherein the conductive patterns are formed such that the interlayer spaces are completely filled with the conductive patterns,

further comprising, before the forming of the tunnel insulating layers:

forming blocking insulating layers on sidewalls of the first holes such that the conductive patterns are covered with the blocking insulating layers; and

forming data storage layers on the blocking insulating layers.

13. The method according to claim 1 , wherein an end of each of the line stacks is patterned in a stepwise shape.

14. The method according to claim 1 , wherein the forming of the block separation layer and the line separation layers comprises forming insulating pillars passing through ends of the respective line stacks.

15. The method according to claim 1 , further comprising forming dummy structures enclosed by the conductive patterns in the ends of the respective line stacks.

16. The method according to claim 15 ,

wherein partial regions of the interlayer spaces in the ends of the respective line stacks are filled with the conductive patterns such that a ring-shaped space is defined in each of the interlayer spaces between the second holes and the conductive patterns, and

wherein the forming of the dummy structures comprises:

forming blocking insulating layers to cover sidewalls of the conductive patterns in the ring-shaped spaces;

forming, on the blocking insulating layers, data storage layers with which the ring-shaped spaces are filled;

forming tunnel insulating layers on sidewalls of the second holes such that the data storage layers are covered with the tunnel insulating layers; and

forming channel layers on the tunnel insulating layers.

17. The method according to claim 15 ,

wherein the interlayer spaces are completely filled with the conductive patterns in the ends of the respective line stacks, and

wherein the forming of the dummy structures comprises:

forming blocking insulating layers on sidewalls of the second holes such that the conductive patterns are covered with the blocking insulating layers;

forming data storage layers on the blocking insulating layers;

forming tunnel insulating layers on the data storage layers; and

forming channel layers on the tunnel insulating layers.

18. The method according to claim 15 , further comprising forming, between the dummy structures, contact plugs that contact the conductive patterns.

19. A method for manufacturing a semiconductor device, comprising:

alternately stacking first material layers and second material layers on a lower structure;

forming first holes passing through the first material layers and the second material layers, each of the first holes defining a channel region;

removing the second material layers through the first holes such that interlayer spaces between the first material layers are formed;

forming, through the first holes, conductive patterns which fill respective interlayer spaces;

forming tunnel insulating layers along sidewalls of the first holes; and

forming channel layers on the tunnel insulating layers, each of the channel layers used as the channel region,

wherein partial regions of the interlayer spaces are filled with the conductive patterns such that a ring-shaped space is defined in each of the interlayer spaces between the tunnel insulating layers and the conductive patterns; and

wherein the ring-shaped space is defined by recessing the conductive patterns before the tunnel insulating layers are formed.

20. A method for manufacturing a semiconductor device, comprising:

alternately stacking first material layers and second material layers on a lower structure;

forming first holes passing through the first material layers and the second material layers, each of the first holes defining a channel region;

removing the second material layers through the first holes such that interlayer spaces between the first material layers are formed;

forming, through the first holes, conductive patterns which fill respective interlayer spaces;

forming tunnel insulating layers along sidewalls of the first holes; and

forming channel layers on the tunnel insulating layers, each of the channel layers being used as the channel region,

wherein the conductive patterns are formed such that the interlayer spaces are completely filled with the conductive patterns, and

wherein before the forming of the tunnel insulating layers:

forming blocking insulating layers on sidewalls of the first holes such that the conductive patterns are covered with the blocking insulating layers; and

forming data storage layers on the blocking insulating layers.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 13, 2017
From: KIM, JAESEONG
To: SK HYNIX INC.
Reel/Frame 042687/0283 →
Priority Claims (1)
KR 10-2016-0149525 · Nov 10, 2016 · national
Continuity (1)
Related Publication 20180130817A1 · May 10, 2018
Cited By (1)
US 12,225,730