Array substrate and display panel

1. An array substrate, comprising:

a substrate;

a first metal layer, disposed on the substrate, the first metal layer forming a gate electrode, a scan line and a first electrode, the scan line extending along a first direction in a plane of a surface of the substrate;

a first insulation layer, disposed on a side of the first metal layer away from the substrate;

a second metal layer, disposed on a side of the first insulation layer away from the first metal layer, the second metal layer forming a second electrode, projections of the first electrode and the second electrode on the substrate at least partly overlapping one anther;

a second insulation layer, disposed on a side of the second metal layer away from the first insulation layer; and

a third metal layer, disposed on a side of the second insulation layer away from the second metal layer,

wherein the third metal layer forms an initialization signal line and a third electrode, projections of the third electrode and the second electrode on the substrate at least partly overlap one another, and the third electrode, the second electrode and the first electrode integratedly form a storage capacitor.

2. An array substrate, comprising:

a substrate;

a first metal layer, disposed on the substrate, the first metal layer forming a gate electrode, a scan line and a first electrode, the scan line extending along a first direction in a plane of a surface of the substrate;

a first insulation layer, disposed on a side of the first metal layer away from the substrate;

a second metal layer, disposed on a side of the first insulation layer away from the first metal layer, the second metal layer forming a second electrode, projections of the first electrode and the second electrode on the substrate at least partly overlapping one anther;

a second insulation layer, disposed on a side of the second metal layer away from the first insulation layer;

a third metal layer, disposed on a side of the second insulation layer away from the second metal layer;

a third insulation layer, disposed on a side of the third metal layer away from the second insulation layer; and

a fourth metal layer, disposed on a side of the third insulation layer away from the third metal layer, wherein the fourth metal layer forms a source electrode, a drain electrode and a data line, and the data line extends along a second direction in a plane of the substrate, and wherein the second direction is perpendicular to the first direction.

3. The array substrate according to claim 2 , wherein the array substrate comprises a plurality of scan lines and a plurality of data lines, the plurality of scan lines intersect the plurality of data lines to define a plurality of pixel regions, wherein the plurality of pixel regions are arranged along the first direction and the second direction in a matrix form.

4. The array substrate according to claim 3 , wherein a pixel driving circuit is disposed in each of the pixel regions, and each of the pixel driving circuit comprises:

a plurality of thin film transistors (TFT) formed of the gate electrode, the source electrode and the drain electrode; and

one said storage capacitor, formed of the first electrode, the second electrode and the third electrode.

5. The array substrate according to claim 4 , wherein one said pixel region intersects only one said scan line.

6. The array substrate according to claim 5 , wherein the pixel driving circuit in each of the pixel regions is configured to receive:

a first scan signal, supplied from the scan line that intersects the pixel region in which the pixel driving circuit is disposed; and

a second scan signal, supplied from the scan line that intersects a previous pixel region adjacent to the pixel region in which the pixel driving circuit is disposed in the second direction.

7. The array substrate according to claim 4 , wherein the fourth metal layer further forms a common power line, and pixel driving circuits of two pixel regions adjacent in the first direction share one said common power line.

8. The array substrate according to claim 4 , wherein the first metal layer further forms a light emitting signal line, and one said pixel region intersects only one said light emitting signal line.

9. A display panel, comprising:

an array substrate; and

a display element, disposed on the array substrate,

wherein the array substrate comprises:

a substrate;

a first metal layer, disposed on the substrate, the first metal layer forming a gate electrode, a scan line and a first electrode, the scan line extending along a first direction in a plane of a surface of the substrate;

a first insulation layer, disposed on a side of the first metal layer away from the substrate;

a second metal layer, disposed on a side of the first insulation layer away from the first metal layer, the second metal layer forming a second electrode, projections of the first electrode and the second electrode on the substrate at least partly overlapping one anther;

a second insulation layer, disposed on a side of the second metal layer away from the first insulation layer; and

a third metal layer, disposed on a side of the second insulation layer away from the second metal layer,

wherein the third metal layer forms an initialization signal line and a third electrode, projections of the third electrode and the second electrode on the substrate at least partly overlap one another, and the third electrode, the second electrode and the first electrode integratedly form a storage capacitor.

10. The display panel according to claim 9 , wherein the display element is an OLED element.

11. The display panel according to claim 9 , wherein a resolution of the display panel is greater than 500 pixels per inch (PPI).

12. The display panel according to claim 9 , wherein the array substrate further comprising:

a third insulation layer, disposed on a side of the third metal layer away from the second insulation layer; and

a fourth metal layer, disposed on a side of the third insulation layer away from the third metal layer, wherein the fourth metal layer forms a source electrode, a drain electrode and a data line, and the data line extends along a second direction in a plane of the substrate, and wherein the second direction is perpendicular to the first direction.

13. The display panel according to claim 12 , wherein the array substrate comprises a plurality of scan lines and a plurality of data lines, the plurality of scan lines intersect the plurality of data lines to define a plurality of pixel regions, wherein the plurality of pixel regions are arranged along the first direction and the second direction in a matrix form.

14. The display panel according to claim 13 , wherein a pixel driving circuit is disposed in each of the pixel regions, and each of the pixel driving circuit comprises:

a plurality of thin film transistors (TFT) formed of the gate electrode, the source electrode and the drain electrode; and

one said storage capacitor, formed of the first electrode, the second electrode and the third electrode.

15. The display panel according to claim 14 , wherein one said pixel region intersects only one said scan line.

16. The display panel according to claim 15 , wherein the pixel driving circuit in each of the pixel regions is configured to receive:

a first scan signal, supplied from the scan line that intersects the pixel region in which the pixel driving circuit is disposed; and

a second scan signal, supplied from the scan line that intersects a previous pixel region adjacent to the pixel region in which the pixel driving circuit is disposed in the second direction.

17. The display panel according to claim 14 , wherein the fourth metal layer further forms a common power line, and pixel driving circuits of two pixel regions adjacent in the first direction share one said common power line.

18. The display panel according to claim 14 , wherein the first metal layer further forms a light emitting signal line, and one said pixel region intersects only one said light emitting signal line.