High-linearity transistors
A transistor includes a first gate-controlled region having a first threshold voltage and a second gate-controlled region in parallel with the first gate-controlled region. The second gate-controlled region has a second threshold voltage different form the first threshold voltage.
1. A transistor, comprising:
at least one gate;
a first gate-controlled region having a first threshold voltage, wherein the first gate-controlled region comprises at least one first semiconductor region controlled by the at least one gate, wherein the at least one first semiconductor region is between respective portions of the at least one gate; and
a second gate-controlled region in parallel with the first gate-controlled region, the second gate-controlled region having a second threshold voltage different form the first threshold voltage, wherein the second gate-controlled region comprises at least one second semiconductor region controlled by the at least one gate, wherein the at least one second semiconductor region is between respective portions of the at least one gate,
wherein the at least one first semiconductor region and the at least one second semiconductor region have different dimensions.
2. The transistor of claim 1 , wherein the transistor is a field effect transistor.
3. The transistor of claim 2 , wherein the field effect transistor is a high electron mobility transistor (HEMT).
4. The transistor of claim 2 , wherein the transistor comprises a III-V semiconductor material.
5. The transistor of claim 1 , further comprising:
a source; and
a drain;
wherein the first and second gate-controlled regions are in parallel between the source and the drain.
6. The transistor of claim 1 , wherein the first gate-controlled region and the second gate-controlled region have different widths.
7. The transistor of claim 6 , wherein the at least one first semiconductor region comprises at least one III-V semiconductor material.
8. The transistor of claim 7 , wherein the at least one first semiconductor region comprises a barrier layer of a first III-V semiconductor material and a region of a second III-V semiconductor material different from the first III-V semiconductor material.
9. The transistor of claim 1 , wherein the first gate-controlled region and the second gate-controlled region have different compositions.
10. The transistor of claim 1 , wherein the first gate-controlled region has a first barrier region and the second gate-controlled region has a second barrier region, wherein the first and second barrier regions have different thicknesses.
11. The transistor of claim 1 , wherein the first gate-controlled region is controlled by a first gate region having a first gate material and the second gate-controlled region is controlled by a second gate region having a second gate material different from the first gate material.
12. The transistor of claim 1 , further comprising a first gate dielectric overlying the first gate-controlled region and a second gate dielectric overlying the second gate-controlled region.
13. The transistor of claim 12 , wherein the first and second gate dielectrics have different thicknesses and/or compositions.
14. The transistor of claim 1 , wherein the first gate-controlled region is controlled by a first gate region and the second gate-controlled region is controlled by a second gate region, and the transistor further comprises a first material overlying the first gate region and a second material overlying the second gate region, the first and second materials having different compositions, doping concentrations and/or thicknesses.
15. The transistor of claim 1 , wherein the first gate-controlled region is controlled by a first gate finger and the second gate-controlled region is controlled by a second gate finger.
16. The transistor of claim 15 , wherein the transistor comprises a plurality of source and drain regions.
17. The transistor of claim 1 , wherein the first and second threshold voltages are offset from one another to reduce g″ m .
18. The transistor of claim 1 , further comprising a third gate-controlled region having a third threshold voltage different from the first threshold voltage and the second threshold voltage.
19. The transistor of claim 18 , wherein the first and second threshold voltages are offset from one another by 0.1-2V and the second and third threshold voltages are offset from one another by 0.1-2V.
20. The transistor of claim 1 , wherein the first gate-controlled region and the second gate-controlled region have different lengths.
21. The transistor of claim 1 , wherein the first gate-controlled region and the second gate-controlled region have different heights.
22. The transistor of claim 1 , wherein the first gate-controlled region and the second gate-controlled region have different cross-sectional areas.
23. A circuit, comprising:
a first transistor having a first threshold voltage, the first transistor having a first gate-controlled region; and
a second transistor in parallel with the first transistor, the second transistor having a second threshold voltage different from the first threshold voltage, the second transistor having a second gate-controlled region,
wherein the first gate-controlled region and the second gate-controlled region have channels of different dimensions between respective portions of at least one gate.
24. A method of forming a transistor, comprising:
forming a first gate-controlled region having a first threshold voltage; and
forming a second gate-controlled region in parallel with the first gate-controlled region, the second gate-controlled region having a second threshold voltage different from the first threshold voltage,
wherein the first gate-controlled region and the second gate-controlled region have channels of different dimensions between respective portions of at least one gate.