System boot code clone

1. A memory device, comprising:

a non-volatile memory configured with a block having a first portion and a second portion, wherein:

the first portion is represented by a first range of physical addresses; and

the second portion is represented by a second range of physical addresses;

an address decoder that maps received command addresses to physical addresses of the non-volatile memory; and

control circuitry configured to maintain a current status indicating whether (i) the first portion of the non-volatile memory is a current area storing information and the second portion of the non-volatile memory is available for being updated with updated information or (ii) the first portion of the non-volatile memory is available for being updated with the updated information and the second portion of the non-volatile memory is the current area storing the information, and to implement an update operation including:

responsive to receiving a write command sequence including a write command address of the block, causing the address decoder to (i) map the write command address to one of the first portion and the second portion, selected in response to the current status and (ii) update the selected one of the first portion and the second portion with the updated information; and

upon completion of the updating of the selected one of the first portion and the second portion, changing the current status to indicate that the selected one of the first portion and the second portion is the current area storing the information and to indicate that the unselected one of the first portion and the second portion is available for being updated with the updated information.

2. The memory device of claim 1 , wherein the unselected one of the first portion and the second portion is write protected until the current status is changed to indicate that the unselected one of the first portion and the second portion is available for being updated with the updated information.

3. The memory device of claim 1 , wherein:

the selected one of the first portion and the second portion remains unlocked for writing until the current status is changed to indicate that the selected one of the first portion and the second portion is the current area storing the information; and

after the current status is changed, the selected one of the first portion and the second portion is write protected.

4. The memory device of claim 1 , wherein the block of the non-volatile memory is a boot block.

5. The memory device of claim 4 , wherein the current area, which is the unselected one of the first portion and the second portion, stores current boot code for booting up a computer system.

6. The memory device of claim 5 , wherein:

an area that is available to be updated with the updated information is from the selected one of the first portion and the second portion; and

the updated information that is used to update the available area is updated boot code.

7. The memory device of claim 6 , wherein the update operation further includes keeping the current area storing the current boot code write protected from a writing operation until the completion of the changing of the current status.

8. The memory device of claim 6 , wherein the update operation further includes keeping the current area storing the current boot code write protected from a writing operation until the completion of the mapping, the updating of the information and the changing of the current status.

9. The memory device of claim 1 , wherein the update operation further includes, upon completion of the changing of the current status, erasing contents of the unselected one of the first portion and the second portion indicated as being available for being updated with the update information.

10. The memory device of claim 1 , wherein the update operation causes the address decoder to map the write command address to one of the first portion and the second portion by one of (i) inverting a most significant bit of the received write command address and (ii) leaving the most significant bit of the received write command address as it is.

11. The memory device of claim 10 , wherein control circuitry determines whether to invert the most significant bit or to leave the most significant bit in dependence upon a status indicator indicating whether to implement a first configuration and a second configuration.

12. The memory device of claim 11 , wherein the control circuitry leaves the most significant bit of the received write command address as it is when the status indicator indicates the first configuration and the control circuitry inverts the most significant bit of the received write command address when the status indicator indicates the second configuration.

13. The memory device of claim 10 , wherein the most significant bit of the received write command address is combined with remaining bits of the received write command address, regardless of whether the most significant bit is inverted or remains as it is.

14. The memory device of claim 13 , wherein the combined most significant bit and the remaining bits of the received write command address are received by the address decoder to map the combined most significant bit and the remaining bits to the one of the first portion and the second portion corresponding to the combined most significant bit and the remaining bits and to update the one of the first portion and the second portion with the updated information.

15. The memory device of claim 1 , wherein the update operation further includes, prior to changing the current status, verifying accuracy of the updated information.

16. The memory device of claim 15 , wherein the accuracy of the updated information written to the selected one of the first portion and the second portion is verified by comparing and detecting differences between (i) the updated information written to the selected one of the first portion and the second portion and (ii) the updated information stored elsewhere.

17. A method of operating a memory device, comprising:

configuring a non-volatile memory of the memory device with a block having a first portion and a second portion, wherein:

the first portion is represented by a first range of physical addresses; and

the second portion is represented by a second range of physical addresses;

mapping, by an address decoder, received command addresses to physical addresses of the non-volatile memory;

maintaining a current status indicating whether (i) the first portion of the non-volatile memory is a current area storing information and the second portion of the non-volatile memory is available for being updated with updated information or (ii) the first portion of the non-volatile memory is available for being updated with the updated information and the second portion of the non-volatile memory is the current area storing the information; and

implementing an update operation including:

responsive to receiving a write command sequence including a write command address of the block, causing the address decoder to (i) map the write command address to one of the first portion and the second portion, selected in response to the current status and (ii) update the selected one of the first portion and the second portion with the updated information; and

upon completion of the updating of the selected one of the first portion and the second portion, changing the current status to indicate that the selected one of the first portion and the second portion is the current area storing the information and to indicate that the unselected one of the first portion and the second portion is available for being updated with the updated information.

18. The method of claim 17 , wherein the update operation further includes, upon completion of the changing of the current status, erasing contents of the unselected one of the first portion and the second portion indicated as being available for being updated with the update information.

19. A method of manufacturing a memory device including:

providing a non-volatile memory configured with a block having a first portion and a second portion, wherein:

the first portion is represented by a first range of physical addresses; and

the second portion is represented by a second range of physical addresses;

providing and configuring an address decoder that maps received command addresses to physical addresses of the non-volatile memory; and

providing control circuitry configured to maintain a current status indicating whether (i) the first portion of the non-volatile memory is a current area storing information and the second portion of the non-volatile memory is available for being updated with updated information or (ii) the first portion of the non-volatile memory is available for being updated with the updated information and the second portion of the non-volatile memory is the current area storing the information, and to implement an update operation including:

responsive to receiving a write command sequence including a write command address block, causing the address decoder to (i) map the write command address to one of the first portion and the second portion, selected in response to the current status and (ii) update the selected one of the first portion and the second portion with the updated information; and

upon completion of the updating of the selected one of the first portion and the second portion, changing the current status to indicate that the selected one of the first portion and the second portion is the current area storing the information and to indicate that the unselected one of the first portion and the second portion is available for being updated with the updated information.

20. The method of claim 19 , wherein the update operation further includes, upon completion of the changing of the current status, erasing contents of the unselected one of the first portion and the second portion indicated as being available for being updated with the update information.