Cell layout utilizing boundary cell with mixed poly pitch within integrated circuit
A cell layout includes a first cell having a plurality of first poly lines extending along a first direction, a second cell having a plurality of second poly lines extending along the first direction, and a boundary cell contiguous with the first cell. The first poly lines have a first uniform poly pitch and the second poly lines have a second uniform poly pitch. The second uniform poly pitch is smaller than the first uniform poly pitch. The boundary cell includes n stripes of first dummy poly lines and m stripes of second dummy poly lines extending along the first direction. The first dummy poly lines have the first uniform poly pitch and the second dummy poly lines have the second uniform pitch.
1. A device, comprising:
an integrated circuit comprising:
a first cell comprising a plurality of first poly lines extending along a first direction, wherein said plurality of first poly lines has a first uniform poly pitch and a first uniform poly line width;
a second cell being spaced apart from said first cell, said second cell comprising a plurality of second poly lines extending along said first direction, wherein said plurality of second poly lines has a second uniform poly pitch and a second uniform poly line width, wherein said second uniform poly pitch is smaller than said first uniform poly pitch; and
a boundary cell being contiguous with said first cell, said boundary cell comprising n stripes of first dummy poly lines and m stripes of second dummy poly lines extending along said first direction, wherein said n stripes of first dummy poly lines have said first uniform poly pitch and said m stripes of second dummy poly lines have said second uniform poly pitch, wherein n and m are both integers, and wherein n and m are both greater than or equal to 2.
2. The device according to claim 1 , wherein said first dummy poly lines and said second dummy poly lines are arranged successively along a second direction that is perpendicular to said first direction.
3. The device according to claim 1 , wherein said first cell is a standard cell chosen from a library of common cells.
4. The device according to claim 1 , wherein said first cell comprises a logic cell.
5. The device according to claim 1 , wherein said second cell is a macro.
6. The device according to claim 1 , wherein said macro comprises an analog macro or a memory macro.
7. The device according to claim 1 , wherein said boundary cell has cell boundaries including a common cell boundary commonly shared with said first cell.
8. The device according to claim 1 , wherein said integrated circuit comprises a portion of an application specific integrated circuit (ASIC) or a system on chip (SoC).
9. The device according to claim 1 , wherein said first uniform poly pitch is 100 nm and said second uniform poly pitch is 90 nm.
10. The device according to claim 1 , wherein said first uniform poly line width is selected from a group consisting of 20, 22, 24, or 28 nm, and said second uniform poly line width is 24 nm.