IP Library Granted Patent US 10,446,671
Granted Patent B2
US 10,446,671 · App. 15/822,284 · Granted Oct 15, 2019

Semiconductor device and manufacturing method thereof

Inventors: Satoru Okamoto (Kanagawa, JP); Shinya Sasagawa (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L29/66969H01L21/385H01L27/1207H01L27/1225H01L27/1255H01L29/22H01L29/24H01L29/401H01L29/408H01L29/42364H01L29/42376H01L29/78H01L29/786H01L29/7869H01L29/78696
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Quick Facts
Patent No.
US 10,446,671
App. No.
15/822,284
Granted
Oct 15, 2019
Kind
B2
Abstract

A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween. The second insulator has an opening and a side surface of the second insulator overlaps with a side surface of the first conductor in the opening with the first insulator positioned therebetween. Part of a surface of the second conductor and part of a surface of the third conductor are in contact with the first insulator in the opening. The oxide semiconductor overlaps with the second conductor and the third conductor.

Claims (55)

1. A semiconductor device comprising:

a first conductor layer and a second conductor layer over an oxide semiconductor;

a third insulator over the first conductor layer and the second conductor layer, the third insulator comprising an opening;

a fourth insulator over the first conductor layer, the second conductor layer, and the oxide semiconductor;

a fifth insulator over the fourth insulator; and

a third conductor over the fifth insulator,

wherein the fourth insulator and the fifth insulator are sandwiched between a side surface of the opening of the third insulator and a side surface of the third conductor, and

wherein in the opening of the third insulator, part of top surfaces of the first conductor layer and the second conductor layer is in contact with the fourth insulator.

2. The semiconductor device according to claim 1 ,

wherein the first conductor layer and the second conductor layer serve as a source electrode and a drain electrode of a transistor,

wherein the fifth insulator serves as a gate insulator of the transistor, and

wherein the third conductor serves as a gate electrode of the transistor.

3. The semiconductor device according to claim 1 , wherein the fourth insulator comprises an oxide comprising at least one of component elements of the oxide semiconductor other than oxygen.

4. The semiconductor device according to claim 1 ,

wherein the third conductor comprises a region serving as a gate electrode of a transistor, and

wherein the transistor has a gate line width of greater than or equal to 5 nm and less than or equal to 60 nm.

5. The semiconductor device according to claim 1 , wherein a surface of the third insulator is leveled with a surface of the third conductor.

6. The semiconductor device according to claim 1 , wherein a surface of the third insulator is leveled with surfaces of the third conductor, the fourth insulator, and the fifth insulator.

7. A semiconductor device comprising:

a first insulator over a substrate;

a second insulator over the first insulator;

an oxide semiconductor over the second insulator;

a first conductor layer and a second conductor layer over the oxide semiconductor;

a third insulator over the first conductor layer and the second conductor layer, the third insulator comprising an opening;

a fourth insulator over the first conductor layer, the second conductor layer, and the oxide semiconductor;

a fifth insulator over the fourth insulator; and

a third conductor over the fifth insulator,

wherein the fourth insulator and the fifth insulator are sandwiched between a side surface of the opening of the third insulator and a side surface of the third conductor, and

wherein in the opening of the third insulator, part of top surfaces of the first conductor layer and the second conductor layer is in contact with the fourth insulator.

8. The semiconductor device according to claim 7 , wherein the second insulator comprises an oxide comprising at least one of component elements of the oxide semiconductor other than oxygen.

9. The semiconductor device according to claim 7 ,

wherein the first conductor layer and the second conductor layer serve as a source electrode and a drain electrode of a transistor,

wherein the fifth insulator serves as a gate insulator of the transistor, and

wherein the third conductor serves as a gate electrode of the transistor.

10. The semiconductor device according to claim 7 , wherein the fourth insulator comprises an oxide comprising at least one of component elements of the oxide semiconductor other than oxygen.

11. The semiconductor device according to claim 7 ,

wherein the third conductor comprises a region serving as a gate electrode of a transistor, and

wherein the transistor has a gate line width of greater than or equal to 5 nm and less than or equal to 60 nm.

12. The semiconductor device according to claim 7 , wherein a surface of the third insulator is leveled with a surface of the third conductor.

13. The semiconductor device according to claim 7 , wherein a surface of the third insulator is leveled with surfaces of the third conductor, the fourth insulator, and the fifth insulator.

14. A semiconductor device comprising:

a first conductor layer and a second conductor layer over an oxide semiconductor;

a third insulator over the first conductor layer and the second conductor layer, the third insulator comprising an opening;

an insulating oxide over the first conductor layer, the second conductor layer, and the oxide semiconductor, wherein the insulating oxide comprises at least one of component elements of the oxide semiconductor other than oxygen;

a gate insulator over the insulating oxide; and

a third conductor over the gate insulator,

wherein the insulating oxide and the gate insulator are sandwiched between a side surface of the opening of the third insulator and a side surface of the third conductor, and

wherein in the opening of the third insulator, part of top surfaces of the first conductor layer and the second conductor layer is in contact with the insulating oxide.

15. The semiconductor device according to claim 14 ,

wherein the first conductor layer and the second conductor layer serve as a source electrode and a drain electrode of a transistor, and

wherein the third conductor serves as a gate electrode of the transistor.

16. The semiconductor device according to claim 14 ,

wherein the third conductor comprises a region serving as a gate electrode of a transistor, and wherein the transistor has a gate line width of greater than or equal to 5 nm and less than or equal to 60 nm.

17. The semiconductor device according to claim 14 , wherein a surface of the third insulator is leveled with a surface of the third conductor.

18. The semiconductor device according to claim 14 , wherein a surface of the third insulator is leveled with surfaces of the third conductor, the insulating oxide, and the gate insulator.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 26, 2018
From: OKAMOTO, SATORU; SASAGAWA, SHINYA
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 044744/0666 →
Priority Claims (1)
JP 2015-041204 · Mar 3, 2015 · national
Continuity (2)
Division 15056356 · Feb 29, 2016
Related Publication 20180108760A1 · Apr 19, 2018
Cited By (2)
US 12,288,799 US 12,402,363