Apparatus and method for at-speed scan test
Described is an apparatus which comprises: a circuitry to selectively switch between a functional clock or a scan clock; a first plurality of circuitries to generate a plurality of pulses according to the scan or functional clocks; and a second plurality of circuitries to generate a plurality of clocks according to the plurality of pulses, wherein the plurality of clocks are for testing one or more circuitries.
1. An apparatus comprising:
a circuitry to selectively switch between a functional clock or a scan clock;
a first plurality of circuitries to generate a plurality of pulses according to the scan or functional clocks;
a second plurality of circuitries to generate a plurality of clocks according to the plurality of pulses, wherein the plurality of clocks are for testing one or more circuitries; and
logic to apply a clock from among the plurality of clocks when a first domain is being tested, and to turn off a clock from among the plurality of clocks for a second domain.
2. The apparatus of claim 1 , wherein the circuitry comprises a second circuitry to generate a multiplexer select signal.
3. The apparatus of claim 2 , wherein the circuitry comprises a multiplexer to provide one of the functional clock or the scan clock according to a logic state of the multiplexer select signal.
4. The apparatus of claim 3 , wherein the second circuitry comprises:
a first shift register chain;
a second shift register chain; and
a logic gate to generate the multiplexer select signal according to outputs of the first and second shift register chains.
5. The apparatus of claim 1 , wherein one of the circuitries of the first plurality of circuitries comprises a first combinational logic to generate a select signal.
6. The apparatus of claim 5 , wherein the one of the circuitries of the first plurality of circuitries comprises a shift register chain including multiplexers controllable by the select signal.
7. The apparatus of claim 6 , wherein the one of the circuitries of the first plurality of circuitries comprises a second combinational logic to generate a pulse according to the scan or functional clocks.
8. The apparatus of claim 1 wherein the second domain is an asynchronous domain.
9. A system comprising:
a memory;
a processor coupled to the memory; and
a wired and wireless interface to allow the processor to communicate with another device, wherein the processor includes an apparatus for at-speed testing of one or more circuitries, wherein the apparatus includes:
a circuitry to selectively switch between a functional clock or a scan clock;
a first plurality of circuitries to generate a plurality of pulses according to the scan or functional clocks; and
a second plurality of circuitries to generate a plurality of clocks according to the plurality of pulses, wherein the plurality of clocks are for testing the one or more circuitries,
wherein the circuitry comprises a second circuitry to generate a multiplexer select signal, and
wherein the second circuitry comprises:
a first shift register chain;
a second shift register chain; and
a logic gate to generate the multiplexer select signal according to outputs of the first and second shift register chains.
10. The system of claim 9 , wherein the processor comprises logic to apply a clock from among the plurality of clocks when a first domain is being tested, and to turn off a clock from among the plurality of clocks when a second domain is an asynchronous domain.
11. The system of claim 9 , wherein the circuitry comprises a multiplexer to provide one of the functional clock or the scan clock according to a logic state of the multiplexer select signal.
12. The system of claim 9 , wherein the second circuitry comprises:
a first shift register chain;
a second shift register chain; and
a logic gate to generate the multiplexer select signal according to outputs of the first and second shift register chains.
13. The system of claim 9 , wherein one of the circuitries of the first plurality of circuitries comprises:
a first combinational logic to generate a select signal;
a shift register chain including multiplexers controllable by the select signal; and
a second combinational logic to generate a pulse according to the scan or functional clocks.
14. A method comprising:
selectively switching between a functional clock or a scan clock;
generating a plurality of pulses according to the scan or functional clocks;
generating a plurality of clocks according to the plurality of pulses;
testing one or more circuitries using the plurality of clocks; and
turning off or gating a clock from among the plurality of clocks when a second domain is an asynchronous domain.
15. The method of claim 14 comprises applying a clock from among the plurality of clocks when a first domain is being tested.
16. The method of claim 14 comprises:
generating a multiplexer select signal; and
providing one of the functional clock or the scan clock according to a logic state of the multiplexer select signal.
17. An apparatus comprising:
a first circuitry for selectively switching between a functional clock or a scan clock;
a second circuitry for generating a plurality of pulses according to the scan or functional clocks;
a third circuitry for generating a plurality of clocks according to the plurality of pulses;
a fourth circuitry for testing one or more circuitries using the plurality of clocks; and
logic to apply a clock from among the plurality of clocks when a first domain is being tested, and to turn off a clock from among the plurality of clocks for a second domain.
18. The apparatus of claim 17 comprises:
a fifth circuitry for generating a multiplexer select signal; and
a sixth circuitry for providing one of the functional clock or the scan clock according to the multiplexer select signal.