Error injection for assessment of error detection and correction techniques using error injection logic and non-volatile memory

1. A memory system, comprising:

a non-volatile memory unit;

a content addressable memory unit coupled to the non-volatile memory unit; and

an error injection logic unit coupled to the non-volatile memory unit and the content addressable memory unit, wherein:

the non-volatile memory unit is programmed to allow a first error injection onto a first data word using the error injection logic unit; and

the error injection logic unit in combination with the content addressable memory unit is configured to replace a bit cell in the memory system.

2. The memory system of claim 1 , wherein:

the error injection logic unit performs the first error injection onto the first data word based on a first data bit of the first data word provided to the error injection logic unit and a first error injection bit provided from the non-volatile memory unit to the error injection logic unit.

3. The memory system of claim 1 , wherein:

the non-volatile memory unit is programmed with a first error injection memory address, the first error injection memory address selected to store the first data word injected with a first error.

4. The memory system of claim 1 , wherein:

the non-volatile memory unit is programmed with an error injection fuse, the error injection fuse being programmed to allow the first error injection onto the first data word.

5. The memory system of claim 1 , wherein:

the non-volatile memory unit is programmed with an error injection memory address fuse that is indicative of a first error injection memory address selected to store the first data word injected with a first error.

6. The memory system of claim 1 , wherein:

a second error injection is performed by the error injection logic unit using a second error injection bit from the non-volatile memory unit.

7. The memory system of claim 1 , wherein:

the first error injection is used to check a performance of at least one error detection and correction code.

8. The memory system of claim 1 , wherein:

the error injection logic unit utilizes a logic gate to flip a first data bit of the first data word from a first state to a second state.

9. The memory system of claim 8 , wherein:

the error injection logic unit performs the first error injection with at least one of a logical exclusive OR gate, a logical NOT-OR (NOR) gate, and a NOT-AND (NAND) gate.

10. A method, comprising:

programming, by an error injection logic unit, a non-volatile memory unit to trigger a first error injection;

providing from a processing unit a first error injection bit to the error injection logic unit;

providing from the processing unit a first data bit of a first data word to the error injection logic unit;

injecting at the error injection logic unit a first error into the first data word using the first error injection bit and the first data bit of the first data word; and

assessing at the error injection logic unit, a performance of an error correction code using the first error injected into the first data word and logic embedded in a content addressable memory unit.

11. The method of claim 10 , further comprising:

programming at the error injection logic unit the non-volatile memory unit with a first error injection memory address, the first error injection memory address selected to store the first data word injected with the first error.

12. The method of claim 11 , wherein:

the first error injection memory address is stored at a content addressable memory.

13. The method of claim 10 , wherein:

programming the non-volatile memory unit to trigger the first error injection is performed using an error injection fuse.

14. The method of claim 10 , wherein:

the error injection logic unit includes a logical exclusive OR gate that is used to flip the first data bit of the first data word from a first bit state to a second bit state.

15. The method of claim 10 , further comprising

providing a second error injection bit to the error injection logic unit, the error injection logic unit using the second error injection bit to inject a second error into the first data word.

16. An error detection and correction evaluation system, comprising:

a memory unit;

a content addressable memory unit coupled to the memory unit;

an error injection logic unit coupled to the content addressable memory unit;

a non-volatile memory unit coupled to the content addressable memory unit and the error injection logic unit; and

a performance evaluation and programming unit coupled to the non-volatile memory unit, wherein:

the non-volatile memory unit is programmed with the performance evaluation and programming unit to allow the error injection logic unit to inject a first error onto a first data word; and the content addressable memory unit to store a first error injection memory address.

17. The error detection and correction evaluation system of claim 16 , wherein:

the error injection logic unit is used to inject the first error onto the first data word using an error injection bit from the non-volatile memory unit and a first data bit from the first data word.

18. The error detection and correction evaluation system of claim 16 , wherein:

the non-volatile memory unit is programmed using an error injection fuse to allow the error injection logic unit to inject the first error onto the first data word.

19. The error detection and correction evaluation system of claim 16 , wherein:

the non-volatile memory unit is programmed with the first error injection memory address, the first error injection memory address selected to store the first data word injected with a first error.

20. The error detection and correction evaluation system of claim 16 , wherein:

the injection of the first error onto the first data word occurs while an application that is not the error injection is running on a central processing unit.