IP Library Granted Patent US 10,452,803
Granted Patent B2
US 10,452,803 · App. 15/418,593 · Granted Oct 22, 2019

Power grid insertion technique

Inventor: Karen Lee Delk (Austin, TX)
Assignee: ARM Limited
G06F17/5077G06F2217/06G06F2217/12
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Quick Facts
Patent No.
US 10,452,803
App. No.
15/418,593
Granted
Oct 22, 2019
Kind
B2
Abstract

Various implementations described herein are directed to an apparatus. The apparatus may include a region identifier module that receives user defined parameters for modifying a power grid layout and identifies a region of the power grid layout for strap insertion based on the user defined parameters. The apparatus may include a track identifier module that identifies track locations in the region of the power grid layout for strap insertion. The apparatus may include a strap placement module that inserts at least one strap in the region of the power grid layout based on pre-determined rules for strap insertion.

Claims (39)

1. An apparatus, comprising:

a region identifier module that receives user defined parameters for modifying a power grid layout and identifies a region of the power grid layout for strap insertion based on the user defined parameters;

a track identifier module that identifies track locations in the region of the power grid layout for strap insertion;

a strap placement module that identifies at least one track location of the track locations in the region of the power grid layout based on pre-determined rules for strap insertion, wherein the strap placement module selects a closest track location to the at least one track location based on the pre-determined rules when the at least one track location is unavailable; and

wherein the strap placement module inserts at least one strap in the closest track location.

2. The apparatus of claim 1 , wherein the power grid layout includes fabrication parameters for applying an integrated circuit design to a semiconductor wafer.

3. The apparatus of claim 2 , wherein the power grid layout identifies parameter variations within the integrated circuit that allow the integrated circuit to function properly when the integrated circuit is etched onto the semiconductor wafer.

4. The apparatus of claim 1 , wherein the region includes a user defined region, and wherein the user defined parameters include the user defined region as provided by a user.

5. The apparatus of claim 1 , wherein the user defined parameters include a supply target pitch as provided by a user.

6. The apparatus of claim 5 , wherein the region of the power grid layout is sub-divided into multiple sub-regions, and wherein the supply target pitch defines a number of the track locations in each of the sub-regions.

7. The apparatus of claim 6 , wherein the strap placement module selects the closest track location to one of a center track location within each sub-region or closest track location to at least one end portion of each sub-region.

8. The apparatus of claim 1 , wherein the track identifier module retrieves a list of each track location in the region, and wherein the list includes data structures that define track information for each track location in the region.

9. The apparatus of claim 8 , wherein the track identifier module identifies obstructions for each track location in the region based on the list of each track location in the region.

10. The apparatus of claim 9 , wherein the obstructions include pre-existing metals and vias in place prior to strap insertion that inhibit strap insertion.

11. The apparatus of claim 1 , wherein the track identifier module identifies one or more blocked tracks having obstructions that inhibit strap insertion.

12. The apparatus of claim 1 , wherein the track identifier module checks spacing rules for strap insertion, and wherein the spacing rules identify adjacent spacing obstructions that inhibit strap insertion for adjacent track locations.

13. The apparatus of claim 1 , wherein the pre-determined rules for strap insertion include avoiding track locations that are blocked with obstructions.

14. The apparatus of claim 1 , wherein the pre-determined rules for strap insertion include avoiding track locations that violate spacing rules for strap insertion.

15. The apparatus of claim 1 , wherein the at least one track location is at least one of a center track location and a track location one end portion of the region.

16. A method, comprising:

receiving user defined parameters from a user for modifying a power grid layout, wherein the power grid layout includes fabrication parameters for applying an integrated circuit design to a semiconductor wafer;

identifying a user defined region of the power grid layout for strap insertion based on the user defined parameters provided by the user;

generating a list of track locations in the user defined region of the power grid layout for strap insertion, including identifying obstructions for each track location in the user defined region of the power grid layout, wherein the obstructions include pre-existing metals and vias in place prior to strap insertion that inhibit strap insertion;

selecting at least one track location of the track locations in the region of the power grid layout based on pre-determined rules for strap insertion;

inserting at least one strap in the selected at least one track location; and

updating the generated list of track location by identifying a new obstruction based on the at least one track location.

17. The method of claim 16 , wherein the power grid layout further identifies parameter variations within the integrated circuit that allow the integrated circuit to function properly when the integrated circuit is etched onto the semiconductor wafer.

18. The method of claim 16 , wherein the user defined parameters include a supply target pitch as provided by a user, and wherein the region of the power grid layout is sub-divided into multiple sub-regions, and wherein the supply target pitch defines a number of the track locations in each of the sub-regions.

19. The method of claim 16 , wherein the pre-determined rules for strap insertion include one or more of:

a first rule that avoids track locations that are blocked with obstructions,

a second rule that avoids track locations that violate spacing rules for strap insertion, and

a third rule that selects track locations closest to a center track location or closest to at least one end portion of the region.

20. A non-transitory computer-readable medium having stored thereon a plurality of computer-executable instructions that, when executed by a computer, cause the computer to:

receive user defined parameters from a user for modifying a power grid layout, wherein the power grid layout includes fabrication parameters for applying an integrated circuit design to a semiconductor wafer;

identify a user defined region of the power grid layout for strap insertion based on the user defined parameters provided by the user;

generate a list of track locations in the user defined region of the power grid layout for strap insertion, including identifying obstructions for each track location in the user defined region of the power grid layout, wherein the obstructions include pre-existing metals and vias in place prior to strap insertion that inhibit strap insertion;

select at least one track location of the track locations in the region of the power grid layout based on pre-determined rules for strap insertion;

insert at least one strap in the selected at least one track location; and

update the generated list of track location by identifying a new obstruction based on the at least one track.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 28, 2017
From: DELK, KAREN LEE
To: ARM LIMITED
Reel/Frame 041549/0392 →
Continuity (1)
Related Publication 20180218106A1 · Aug 2, 2018