IP Library › Granted Patent US 10,453,612
Granted Patent B2
US 10,453,612 · App. 15/846,369 · Granted Oct 22, 2019

Multilayer ceramic capacitor

Inventors: Yosuke Terashita (Nagaokakyo, JP); Hidetaka Sugiyama (Nagaokakyo, JP)
Assignee: MURATA MANUFACTURING CO., LTD.
H01G4/248H01G4/008H01G4/30
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Quick Facts
Patent No.
US 10,453,612
App. No.
15/846,369
Granted
Oct 22, 2019
Kind
B2
Abstract

A multilayer ceramic capacitor includes a laminate and first and second external electrodes that each include first and second underlying electrode layers, first and second conductive resin layers, and first and second plating layers. The first underlying electrode layer includes a portion not covered with the first conductive resin layer on an end surface of the laminate, and the first plating layer is disposed on a surface of the portion of the first underlying electrode layer. The second underlying electrode layer includes a portion not covered with the second conductive resin layer on an end surface of the laminate, and the second plating layer is disposed on a surface of the portion of the second underlying electrode layer.

Claims (32)

1. A multilayer ceramic capacitor comprising:

a laminate including a plurality of dielectric layers, a first main surface and a second main surface facing each other and stacked in a stacking direction, a first side surface and a second side surface facing each other in a width direction orthogonal or substantially orthogonal to the stacking direction, and a first end surface and a second end surface facing each other in a length direction orthogonal or substantially orthogonal to the stacking direction and the width direction;

a first internal electrode exposed from the first end surface and a second internal electrode exposed from the second end surface, the first internal electrode and the second internal electrode being alternately stacked with one of the dielectric layers interposed therebetween;

a first external electrode connected to the first internal electrode and disposed on a surface of the first end surface, portions of surfaces of the first main surface and the second main surface, and portions of surfaces of the first side surface and the second side surface; and

a second external electrode connected to the second internal electrode and disposed on a surface of the second end surface, portions of the surfaces of the first main surface and the second main surface, and portions of the surfaces of the first side surface and the second side surface; wherein

the first external electrode includes:

a first underlying electrode layer including conductive metal and a glass component;

a first conductive resin layer disposed on a surface of the first underlying electrode layer and including a thermosetting resin and metal; and

a first plating layer disposed on a surface of the first conductive resin layer;

the second external electrode includes:

a second underlying electrode layer including conductive metal and a glass component;

a second conductive resin layer disposed on a surface of the second underlying electrode layer and including a thermosetting resin and metal; and

a second plating layer disposed on a surface of the second conductive resin layer;

the first underlying electrode layer includes on the first end surface a portion not covered with the first conductive resin layer;

the first plating layer is disposed on a surface of the portion of the first underlying electrode layer, which is not covered with the first conductive resin layer;

the second underlying electrode layer includes on the second end surface a portion not covered with the second conductive resin layer;

the second plating layer is disposed on a surface of the portion of the second underlying electrode layer, which is not covered with the second conductive resin layer;

each of the first and second conductive resin layers is in direct contact with the laminate on one or more of the first and second main surfaces and the first and second side surfaces of the laminate;

a front end portion of the first conductive resin layer disposed on the first underlying electrode layer on the first and second main surfaces and the first and second side surfaces overlaps within a range of not less than about 10 μm in a direction of the second end surface from a front end portion of the first underlying electrode layer to be disposed on the surface of the laminate; and

a front end portion of the second conductive resin layer disposed on the second underlying electrode layer on the first and second main surfaces and the first and second side surfaces overlaps within a range of not less than about 10 μm in a direction of the first end surface from a front end portion of the second underlying electrode layer to be disposed on the surface of the laminate.

2. The multilayer ceramic capacitor according to claim 1 , wherein

the first conductive resin layer is provided on a surface of the first underlying electrode layer located on a ridge line portion and a corner portion defined by each intersection of the first end surface, the first main surface, the second main surface, the first side surface and the second side surface of the laminate; and

the second conductive resin layer is provided on a surface of the second underlying electrode layer located on a ridge line portion and a corner portion defined by each intersection of the second end surface, the first main surface, the second main surface, the first side surface and the second side surface of the laminate.

3. The multilayer ceramic capacitor according to claim 1 , wherein an exposure ratio of the portion of the first underlying electrode layer on the first end surface, which is not covered with the first conductive resin layer, and an exposure ratio of the portion of the second underlying electrode layer on the second end surface, which is not covered with the second conductive resin layer, are not less than about 5%.

4. The multilayer ceramic capacitor according to claim 1 , wherein an exposure ratio of the portion of the first underlying electrode layer on the first end surface, which is not covered with the first conductive resin layer, and an exposure ratio of the portion of the second underlying electrode layer on the second end surface, which is not covered with the second conductive resin layer, are not less than about 30%.

5. The multilayer ceramic capacitor according to claim 1 , wherein an exposure ratio of the portion of the first underlying electrode layer on the first end surface, which is not covered with the first conductive resin layer, and an exposure ratio of the portion of the second underlying electrode layer on the second end surface, which is not covered with the second conductive resin layer, are not less than about 30% and not more than about 82%.

6. The multilayer ceramic capacitor according to claim 1 , wherein

the first underlying electrode layer disposed on the surface of the first end surface has a thickness at a central portion of the first end surface that is larger than a thickness of other portions of the first underlying electrode layer; and

the second underlying electrode layer disposed on the surface of the second end surface has a thickness at a central portion of the second end surface is larger than a thickness of other portions of the second underlying electrode layer.

7. The multilayer ceramic capacitor according to claim 1 , wherein a shape of each of the portion of the first underlying electrode layer not covered with the first conductive resin layer and the portion of the second underlying electrode layer not covered with the second conductive resin layer is circular, substantially circular, elliptical, or substantially elliptical.

8. The multilayer ceramic capacitor according to claim 1 , wherein the conductive metal of the first and second underlying electrode layers includes at least one selected from Cu, Ni, Ag, Pd, Ag—Pd alloy, and Au, and the glass of the first and second underlying electrode layers includes at least one selected from B, Si, Ba, Mg, Al, and Li.

9. The multilayer ceramic capacitor according to claim 1 , wherein a thickness of each of the first and second conductive resin layers is not less than about 0.5 μm and not more than about 20 μm.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 19, 2017
From: TERASHITA, YOSUKE; SUGIYAMA, HIDETAKA
To: MURATA MANUFACTURING CO., LTD.
Reel/Frame 044432/0865 →
Priority Claims (1)
JP 2016-247912 · Dec 21, 2016 · national
Continuity (1)
Related Publication 20180174753A1 · Jun 21, 2018
Cited By (2)
US 12,531,187 US 12,592,340