IP Library › Granted Patent US 10,453,614
Granted Patent B2
US 10,453,614 · App. 15/679,063 · Granted Oct 22, 2019

Multilayer ceramic capacitor and manufacturing method of multilayer ceramic capacitor

Inventors: Tomoaki Nakamura (Takasaki, JP); Mikio Tahara (Takasaki, JP)
Assignee: TAIYO YUDEN CO., LTD.
H01G4/30H01G4/2325H01G4/248H01G4/008H01G4/12H01G4/1227
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Quick Facts
Patent No.
US 10,453,614
App. No.
15/679,063
Granted
Oct 22, 2019
Kind
B2
Abstract

A multilayer ceramic capacitor includes: a multilayer chip having a parallelepiped shape in which each of a plurality of ceramic dielectric layers and each of a plurality of internal electrode layers are alternately stacked and are alternately exposed to two edge faces of the multilayer chip; and a pair of external electrodes that are formed from the two edge faces to at least one of side faces of the multilayer chip; wherein in the external electrodes, a first metal layer whose ceramic amount is 5 wt % or more contacts with the two edge faces, and a second metal layer whose ceramic amount is less than 5 wt % contacts with the at least one of the side faces.

Claims (19)

1. A multilayer ceramic capacitor comprising:

a multilayer chip having a parallelepiped shape in which each of a plurality of ceramic dielectric layers and each of a plurality of internal electrode layers are alternately stacked and the plurality of internal electrode layers is each alternately exposed to two edge faces of the multilayer chip; and

a pair of external electrodes that are formed from the two edge faces to at least one of side faces of the multilayer chip;

wherein in the external electrodes, a first metal layer whose glass component amount is 5 wt % or more contacts the two edge faces and does not extend to the at least one of side faces, and a second metal layer contacts the at least one of the side faces,

wherein the second metal layer includes a glass component, and the amount of the glass component in the second metal layer is less than 5 wt %, and

wherein a main component of each of the first metal layer and the second metal layer is Cu.

2. The multilayer ceramic capacitor as claimed in claim 1 , wherein the second metal layer is a sintered layer.

3. The multilayer ceramic capacitor as claimed in claim 1 , wherein the multilayer chip has a first cover layer and a second cover layer as outermost layers in a stacking direction of the ceramic dielectric layers, wherein the second metal layer contacts the first cover layer and the second cover layer at the two edge faces of the multilayer chip.

4. A manufacturing method of a multilayer ceramic capacitor comprising:

forming a ceramic multilayer structure having a parallelepiped shape by alternately stacking ceramic dielectric green sheets and conductive pastes for forming internal electrodes and alternately exposing the conductive pastes to two edge faces of the ceramic multilayer structure;

forming a multilayer chip by baking the ceramic multilayer structure;

providing a first metal paste including a glass component so as to contact the two edge faces without extending to at least one of side faces of the multilayer chip;

providing a second metal paste including less glass component than the first metal paste so as to contact the first metal paste and the at least one of side faces of the multilayer chip; and

forming a first metal layer and a second metal layer by baking the first metal paste and the second metal paste, the first metal layer including 5 wt % or more of glass component and contacting the two edge faces, the second metal layer contacting the at least one of the side faces, wherein the second metal layer includes glass component, and the amount of the glass component in the second metal layer is less than 5 wt % and wherein a main component of each of the first metal layer and the second metal layer is Cu.

5. A manufacturing method of a multilayer ceramic capacitor comprising:

forming a ceramic multilayer structure having a parallelepiped shape by alternately stacking ceramic dielectric green sheets and conductive pastes for forming internal electrodes and alternately exposing the conductive pastes to two edge faces of the ceramic multilayer structure;

providing a first metal paste including a glass component so as to contact the two edge faces without extending to at least one of side faces of the ceramic multilayer structure;

providing a second metal paste including less glass component than the first metal paste so as to contact the first metal paste and contact the at least one of side faces of the ceramic multilayer structure; and

forming a first metal layer and a second metal layer by baking a resulting ceramic multilayer structure, the first metal layer including 5 wt % or more of glass component and contacting the two edge faces, the second metal layer contacting the at least one of the side faces, wherein the second metal layer includes glass component, and the amount of the glass component in the second metal layer is less than 5 wt %, and wherein a main component of each of the first metal layer and the second metal layer is Cu.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 16, 2017
From: NAKAMURA, TOMOAKI; TAHARA, MIKIO
To: TAIYO YUDEN CO., LTD.
Reel/Frame 043311/0895 →
Priority Claims (1)
JP 2016-165015 · Aug 25, 2016 · national
Continuity (1)
Related Publication 20180061576A1 · Mar 1, 2018