Power electronics assemblies with cio bonding layers and double sided cooling, and vehicles incorporating the same

1. A 2-in-1 power electronics assembly comprising:

a frame comprising a lower dielectric layer, an upper dielectric layer spaced apart from the lower dielectric layer, and a sidewall disposed between and coupled to the lower dielectric layer and the upper dielectric layer, wherein the lower dielectric layer comprises a lower cooling fluid inlet and the upper dielectric layer comprises an upper cooling fluid outlet;

a first semiconductor device assembly disposed within the frame and comprising a first semiconductor device disposed between a first lower MIO layer and a first upper MIO layer;

a second semiconductor device assembly disposed within the frame and comprising a second semiconductor device disposed between a second lower MIO layer and a second upper MIO layer, wherein the second semiconductor device is spaced apart from the first semiconductor device assembly;

a middle dielectric layer positioned between the upper dielectric layer, the lower dielectric layer, the first semiconductor device assembly, and the second semiconductor device assembly;

a lower fluid chamber disposed between the lower dielectric layer, the middle dielectric layer, the first semiconductor device assembly and the second semiconductor device assembly; and

an upper fluid chamber disposed between the upper dielectric layer, the middle dielectric layer, the first semiconductor device assembly and the second semiconductor device assembly.

2. The 2-in-1 power electronics assembly of claim 1 , wherein the lower dielectric layer further comprises a lower cooling fluid outlet and the upper dielectric layer further comprises an upper cooling fluid inlet.

3. The 2-in-1 power electronics assembly of claim 2 , further comprising:

a lower cooling fluid circuit comprising the lower cooling fluid inlet, the second lower MIO layer, the lower fluid chamber, the first lower MIO layer and the lower cooling fluid outlet, wherein the lower cooling fluid circuit is configured for cooling fluid to flow proximate to first surfaces of the first semiconductor device and the second semiconductor device; and

an upper cooling fluid circuit comprising the upper cooling fluid inlet, the first upper MIO layer, the upper fluid chamber, the second upper MIO layer and the upper cooling fluid outlet, wherein the upper cooling fluid circuit is configured for cooling fluid to flow proximate to second surfaces of the first semiconductor device and the second semiconductor device.

4. The 2-in-1 power electronics assembly of claim 2 , further comprising a positive electrode disposed between the upper dielectric layer and the first upper MIO layer, a negative electrode disposed between the upper dielectric layer and the second upper MIO layer, and an output electrode disposed between the lower dielectric layer, the first lower MIO layer and the second lower MIO layer, wherein:

the positive electrode is in electrical communication with the first semiconductor device through the first upper MIO layer;

the negative electrode is in electrical communication with the second semiconductor device through the second upper MIO layer; and

the output electrode is in electrical communication with the first semiconductor device and the second semiconductor device through the first lower MIO layer and the second lower MIO layer, respectively.

5. The 2-in-1 power electronics assembly of claim 2 , further comprising:

a first isolating MIO layer spaced apart from the first lower MIO layer and disposed between the first semiconductor device and the lower dielectric layer; and

a first gate electrode disposed between the lower dielectric layer and the first isolating MIO layer, wherein the first gate electrode is electrically isolated from an output electrode and in electrical communication with the first semiconductor device through the first isolating MIO layer.

6. The 2-in-1 power electronics assembly of claim 2 , further comprising:

a second isolating MIO layer spaced apart from the second upper MIO layer and disposed between the second semiconductor device and the upper dielectric layer; and

a second gate electrode disposed between the upper dielectric layer and the second isolating MIO layer, wherein the second gate electrode is electrically isolated from a negative electrode and in electrical communication with the second semiconductor device through the second isolating MIO layer.

7. The 2-in-1 power electronics assembly of claim 1 , wherein:

the lower cooling fluid inlet of the lower dielectric layer comprises a first lower cooling fluid inlet and a second lower cooling fluid inlet;

the upper cooling fluid outlet of the upper dielectric layer comprises a first upper cooling fluid outlet and a second upper cooling fluid outlet; and

a fluid path extends through the middle dielectric layer between the lower fluid chamber and the upper fluid chamber.

8. The 2-in-1 power electronics of claim 7 , wherein the fluid path comprises an MIO column extending through the middle dielectric layer.

9. The 2-in-1 power electronics of claim 7 , wherein the fluid path comprises at least one metal through hole via extending through the middle dielectric layer.

10. The 2-in-1 power electronics of claim 7 , further comprising a cooling fluid circuit configured for cooling fluid to flow proximate to surfaces of the first semiconductor device and the second semiconductor device, the cooling fluid circuit comprising the first and second lower cooling fluid inlets, the lower fluid chamber, the first and second lower MIO layers, the fluid path extending through the middle dielectric layer, the upper fluid chamber, the first and second upper MIO layers, and the first and second upper cooling fluid outlets.

11. The 2-in-1 power electronics of claim 10 wherein:

a first portion of the cooling fluid circuit comprises a first fluid flow path of: first lower cooling fluid inlet—first lower MIO layer—lower fluid chamber—fluid path—first upper MIO layer—first upper cooling fluid outlet; and

a second portion of the cooling fluid circuit comprises a second fluid flow path of: second lower cooling fluid inlet—second lower CIO layer—fluid path—upper fluid chamber—second upper MIO layer—second upper cooling fluid outlet.

12. The 2-in-1 power electronics of claim 7 , further comprising a positive electrode disposed between the lower dielectric layer and the first lower MIO layer, a negative electrode disposed between the upper dielectric layer and the second upper MIO layer, a first output electrode disposed between the upper dielectric layer and the first upper MIO layer, and a second output electrode disposed between the lower dielectric layer and the second lower MIO layer, wherein the positive electrode is in electrical communication with the first semiconductor device through the first lower MIO layer, the negative electrode is in electrical communication with the first semiconductor device through the second upper MIO layer, the first output electrode is in electrical communication with the first semiconductor device through the first upper MIO layer, and the second output electrode is in electrical communication with the second semiconductor device through the second lower MIO layer.

13. A 2-in-1 power electronics assembly comprising:

a lower dielectric layer comprising a lower cooling fluid inlet and a lower cooling fluid outlet;

an upper dielectric layer spaced apart from the lower dielectric layer and comprising an upper cooling fluid inlet and an upper cooling fluid outlet;

a middle dielectric layer positioned between and spaced apart from the lower dielectric layer and the upper dielectric layer;

a first semiconductor device assembly comprising a first semiconductor device disposed between a first lower MIO layer and a first upper MIO layer;

a second semiconductor device assembly spaced apart from the first semiconductor device assembly and comprising a second semiconductor device disposed between a second lower MIO layer and a second upper MIO layer;

a lower fluid chamber disposed between the lower dielectric layer, the middle dielectric layer, the first semiconductor device assembly, and the second semiconductor device assembly; and

an upper fluid chamber disposed between the middle dielectric layer, the upper dielectric layer, the first semiconductor device assembly, and the second semiconductor device assembly, wherein:

the first semiconductor device assembly and the second semiconductor device assembly are disposed between the lower dielectric layer and the upper dielectric layer; and

the middle dielectric layer is positioned between the first semiconductor device assembly and the second semiconductor device assembly.

14. The 2-in-1 power electronics assembly of claim 13 , further comprising:

a lower cooling fluid circuit comprising a lower cooling fluid path of: lower cooling fluid inlet—second lower MIO layer—lower fluid chamber—first lower MIO layer—lower cooling fluid outlet; and

an upper cooling fluid circuit comprising an upper cooling fluid path of: upper cooling fluid inlet—first upper MIO layer—upper fluid chamber—second upper MIO layer—upper cooling fluid outlet.

15. The 2-in-1 power electronics assembly of claim 13 , further comprising a positive electrode disposed between the upper dielectric layer and the first upper MIO layer, a negative electrode disposed between the upper dielectric layer and the second upper MIO layer, and an output electrode disposed between the lower dielectric layer, the first lower MIO layer and the second lower MIO layer, wherein:

the positive electrode is in electrical communication with the first semiconductor device through the first upper MIO layer;

the negative electrode is in electrical communication with the second semiconductor device through the second upper MIO layer; and

the output electrode is in electrical communication with the first semiconductor device and the second semiconductor device through the first lower MIO layer and the second lower MIO layer, respectively.

16. The 2-in-1 power electronics assembly of claim 15 , further comprising:

a first isolating MIO layer spaced apart from the first lower MIO layer and disposed between the first semiconductor device and the lower dielectric layer;

a first gate electrode disposed between the lower dielectric layer and the first isolating MIO layer, wherein the first gate electrode is electrically isolated from the output electrode and in electrical communication with the first semiconductor device through the first isolating MIO layer;

a second isolating MIO layer spaced apart from the second upper MIO layer and disposed between the second semiconductor device and the upper dielectric layer; and

a second gate electrode disposed between the upper dielectric layer and the second isolating MIO layer, wherein the second gate electrode is electrically isolated from the negative electrode and in electrical communication with the second semiconductor device through the second isolating MIO layer.

17. A 2-in-1 power electronics assembly comprising:

a lower dielectric layer comprising a first lower cooling fluid inlet and a second lower cooling fluid inlet;

an upper dielectric layer spaced apart from the lower dielectric layer and comprising a first upper cooling fluid outlet and a second cooling fluid outlet;

a middle dielectric layer positioned between and spaced apart from the lower dielectric layer and the upper dielectric layer;

a fluid path extending through the middle dielectric layer;

a first semiconductor device assembly comprising a first semiconductor device disposed between a first lower MIO layer and a first upper MIO layer;

a second semiconductor device assembly spaced apart from the first semiconductor device assembly and comprising a second semiconductor device disposed between a second lower MIO layer and a second upper MIO layer;

a lower fluid chamber disposed between the lower dielectric layer and the middle dielectric layer; and

an upper fluid chamber disposed between the middle dielectric layer and the upper dielectric layer, wherein:

the first semiconductor device assembly and the second semiconductor device assembly are disposed between the lower dielectric layer and the upper dielectric layer; and

the middle dielectric layer is positioned between the first semiconductor device assembly and the second semiconductor device assembly.

18. The 2-in-1 power electronics of claim 17 wherein:

a first portion of a cooling fluid circuit comprises a first fluid flow path of: first lower cooling fluid inlet—first lower CIO layer—lower fluid chamber—fluid path—first upper MIO layer—first upper cooling fluid outlet; and

a second portion of the cooling fluid circuit comprises a second fluid flow path of: second lower cooling fluid inlet—second lower CIO layer—fluid path—upper fluid chamber—second upper MIO layer—second upper cooling fluid outlet.

19. The 2-in-1 power electronics of claim 17 , further comprising a positive electrode disposed between the lower dielectric layer and the first lower MIO layer, a negative electrode disposed between the upper dielectric layer and the second upper MIO layer, a first output electrode disposed between the upper dielectric layer and the first upper MIO layer, and a second output electrode disposed between the lower dielectric layer and the second lower MIO layer, wherein:

the positive electrode is in electrical communication with the first semiconductor device through the first lower MIO layer;

the negative electrode is in electrical communication with the second semiconductor device through the second upper MIO layer;

the first output electrode is in electrical communication with the first semiconductor device through the first upper MIO layer; and

the second output electrode is in electrical communication with the second semiconductor device through the second lower MIO layer.

20. The 2-in-1 power electronics assembly of claim 19 , further comprising:

a first isolating MIO layer spaced apart from the first upper MIO layer and disposed between the first semiconductor device and the upper dielectric layer;

a first gate electrode disposed between the upper dielectric layer and the first isolating MIO layer, wherein the first gate electrode is electrically isolated from the first output electrode and in electrical communication with the first semiconductor device through the first isolating MIO layer;

a second isolating MIO layer spaced apart from the second upper MIO layer and disposed between the second semiconductor device and the upper dielectric layer; and

a second gate electrode disposed between the upper dielectric layer and the second isolating MIO layer, wherein the second gate electrode is electrically isolated from the negative electrode and in electrical communication with the second semiconductor device through the second isolating MIO layer.